Kazutoshi Kobayashi

Profile Information

Affiliation: Kyoto Institute of Technology

Degree: 博士(工学)(京都大学)

Other name(s) (e.g. nickname): 小林
Researcher number: 70252476
ORCID ID: https://orcid.org/0000-0002-7139-7274
J-GLOBAL ID: 201101002132444969
researchmap Member ID: B000219304

External link: http://kaken.nii.ac.jp/ja/r/70252476

略歴
京都府立嵯峨野高校卒業(1987/03)
京都大学工学部電子工学科卒業(1991/03)
京都大学大学院工学研究科電子工学修了(1993/03)
京都大学大学院工学研究科電子工学科，情報学研究科通信情報システム専攻助手(1993/04-2001/03)
京都大学大学院情報学研究科通信情報システム専攻助教授/准教授(2001/04-2002/03, 2004/04-2009/03)
東京大学大規模集積システム設計教育研究センター助教授(2002/04-2004/03)
京都工芸繊維大学電子システム工学専攻教授(2009/04-)

Major Research Interests

Research Areas

Research History

2009 - Present

Professor, Graduate School of Science and Technology, Kyoto Institute of Technology
Apr, 2004 - Mar, 2009

Associate Professor, Graduate School of Informatics Department of Communications and Computer Engineering, Kyoto University
Apr, 2002 - Mar, 2004

VLSI (Very Scale Integration Large) Design and Education Center, The University of Tokyo
Apr, 2001 - Mar, 2002

Associate Professor, Graduate School of Informatics Department of Communications and Computer Engineering, Kyoto University
Apr, 1998 - Mar, 2001

Assistant Professor, Graduate School of Informatics Department of Communications and Computer Engineering, Kyoto University
Apr, 1993 - Mar, 1998

Assistant Professor, Graduate School of Engineering Department of Electronic Science and Engineering, Kyoto University

Education

Apr, 1991 - Mar, 1993

Department of Electronic Science and Engineering, Graduate School of Engineering, Kyoto University
Apr, 1987 - Mar, 1991

Department of Electronics, Faculty of Engineering, Kyoto University

Awards

Sep, 2021

Electronics Society Award, Institute of Electronics, Information and Communication Engineers

Papers

324

The Contribution of Secondary Particles Following Carbon Ion Radiotherapy to Soft Errors in CIEDs

Yudai Kawakami, Makoto Sakai, Hiroaki Masuda, Masami Miyajima, Takao Kanzaki, Kazutoshi Kobayashi, Tatsuya Ohno, Hiroshi Sakurai

IEEE Open Journal of Engineering in Medicine and Biology, 2024
Nonvolatile Storage Cells Using FiCC for IoT Processors with Intermittent Operations

Yuki ABE, Kazutoshi KOBAYASHI, Jun SHIOMI, Hiroyuki OCHI

IEICE Transactions on Electronics, E106.C(10) 546-555, Oct 1, 2023 Peer-reviewed
Frequency Dependency of Soft Error Rates Based on Dynamic Soft Error Measurements

Haruto Sugisaki, Ryuichi Nakajima, Shotaro Sugitani, Jun Furuta, Kazutoshi Kobayashi

2023 International Conference on IC Design and Technology (ICICDT), Sep 25, 2023 Peer-reviewed
SEU Sensitivity of PMOS and NMOS Transistors in a 65 nm Bulk Process by α-Particle Irradiation

Keita Yoshida, Ryuichi Nakajima, Shotaro Sugitani, Takafumi Ito, Jun Furuta, Kazutoshi Kobayashi

2023 International Conference on IC Design and Technology (ICICDT), Sep 25, 2023 Peer-reviewed
Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing

Yoshisato Yokoyama, Koji Nii, Yuichiro Ishii, Shinji Tanaka, Kazutoshi Kobayashi

IEEE Journal of Solid-State Circuits, 58(7) 2098-2108, Jul 1, 2023 Peer-reviewed
Ultra Long-term Measurement Results of BTI-induced Aging Degradation on 7-nm Ring Oscillators

Kazutoshi Kobayashi, Tomoharu Kishita, Hiroki Nakano, Jun Furuta, Mitsuhiko Igarashi, Shigetaka Kumashiro, Michitarou Yabuuchi, Hironori Sakamoto

IEEE International Reliability Physics Symposium Proceedings, 2023-March, 2023 Peer-reviewed
Radiation Hardened Flip-Flops with low Area, Delay and Power Overheads in a 65 nm bulk process

Shotaro Sugitani, Ryuichi Nakajima, Keita Yoshida, Jun Furuta, Kazutoshi Kobayashi

IEEE International Reliability Physics Symposium Proceedings, 2023-March, 2023 Peer-reviewed
Radiation Hardness Evaluations of a Stacked Flip Flop in a 22 nm FD-SOI Process by Heavy-Ion Irradiation

Shotaro Sugitani, Ryuichi Nakajima, Takafumi Ito, Jun Furuta, Kazutoshi Kobayashi, Mathieu Louvat, Francois Jacquet, Jean Christophe Eloy, Olivier Montfort, Lionel Jure …

Proceedings - 2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design, IOLTS 2023, 2023 Peer-reviewed
A 13-bit Radiation-Hardened SAR-ADC with Error Correction by Adaptive Topology Transformation

Yuya Aoki, Tatsuya Iwata, Takuji Miki, Kazutoshi Kobayashi, Takefumi Yoshikawa

IEEE International Reliability Physics Symposium Proceedings, 2023-March, 2023 Peer-reviewed
A Terrestrial SER Estimation Methodology based on Simulation coupled with One-Time Neutron Irradiation Testing

Shin-ichiro Abe, Masanori Hashimoto, Wang Liao, Takashi Kato, Hiroaki Asai, Kenichi Shimbo, Hideya Matsuyama, Tatsuhiko Sato, Kazutoshi Kobayashi, Yukinobu Watanabe

IEEE Transactions on Nuclear Science, 1-1, 2023 Peer-reviewed
A Three-Level GaN Driver for High False Turn-ON Tolerance With Minimal Reverse Conduction Loss

Takehiro Takahashi, Takumi Takehisa, Jun Furuta, Michihiro Shintani, Kazutoshi Kobayashi

IEEE Open Journal of Power Electronics, 4 357-366, 2023
Nonvolatile Flip-Flops Using FiCC for IoT Processors with Intermittent Operations

Yuki Abe, Kazutoshi Kobayashi, Hiroyuki Ochi

2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS), Aug 7, 2022
Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations

Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi

2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), Apr 20, 2022 Last authorCorresponding author
An Aging Degradation Suppression Scheme at Constant Performance by Controlling Supply Voltage and Body Bias in a 65 nm Fully-Depleted Silicon-On-Insulator Process

Ikuo Suda, Ryo Kishida, Kazutoshi Kobayashi

2022 IEEE International Reliability Physics Symposium (IRPS), Mar, 2022
Radiation Hardened Flip-Flops Minimizing Area, Power, and Delay Overheads with 1/100 Lower α-SER in a 130 nm Bulk Process

Ryuichi Nakajima, Kazuya Ioki, Jun Furuta, Kazutoshi Kobayashi

Proceedings - 2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design, IOLTS 2022, 2022
Evaluation of Soft Error Tolerance on Flip-Flops Restoring from a Single Node Upset by C-elements

Takafumi Ito, Ryuichi Nakajima, Jun Furuta, Kazutoshi Kobayashi

2022 IEEE International Meeting for Future of Electron Devices, Kansai, IMFEDK 2022, 2022
A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment

Takefumi Yoshikawa, Masahiro Ishimaru, Tatsuya Iwata, Fuma Mori, Kazutoshi Kobayashi

Journal of Electronic Testing: Theory and Applications (JETTA), 2022
間欠動作を行うIoT向けプロセッサに適したFiCCを用いた不揮発スタンダードセルメモリの実測評価

阿部佑貴, 小林和淑, 塩見準, 越智裕之

DAシンポジウム, 3-8, Sep, 2021
130nmプロセスによるフリップフロップのソフトエラー耐性向上手法の提案

中島隆一, 井置一哉, 小谷萌香, 古田潤, 小林和淑

DAシンポジウム, 148-153, Sep, 2021 Last author
FDSOIプロセスにおける遅延を増加させたガードゲート型フリップフロップのソフトエラー耐性の実測評価

記伊智也, 古田潤, 小林和淑

DAシンポジウム, 155-159, Sep, 2021 Last author

Misc.

219

Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model

Takuya Komawaki, Michitarou Yabuuchi, Ryo Kishida, Jun Furuta, Takashi Matsumoto, Kazutoshi Kobayashi

IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, E-100A(12) 2758-2763, Dec, 2017 Peer-reviewedLast author
An accurate metric to control time step of transient device simulation by matrix exponential method

Shigetaka Kumashiro, Tatsuya Kamei, Akira Hiroki, Kazutoshi Kobayashi

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 2017-September 37-40, Oct 25, 2017 Peer-reviewedLast author
Analysis of Neutron-induced Soft Error Rates on 28nm FD-SOI and 22nm FinFET Latches by the PHITS-TCAD Simulation System

Jun Furuta, Shigehiro Umehara, Kazutoshi Kobayashi

IEEE International Conference on Simulation of Semiconductor Processes and Devices, 2017- 185-188, Sep, 2017 Peer-reviewedLast author
MHz-Switching-Speed Current-Source Gate Driver for SiC Power MOSFETs

Sho Inamori, Jun Furuta, Kazutoshi Kobayashi

European Conference on Power Electronics and Applications, 2017-January DS1a.2.1-2.7, Sep, 2017 Peer-reviewedLast author
Design of RCD Snubber Considering Wiring Inductance for MHz-Switching of SiC-MOSFET

Yuki Yamashita, Jun Furuta, Sho Inamori, Kazutoshi Kobayashi

IEEE Workshop on Control and Modeling for Power Electronics, (O10-2), Jul, 2017 Peer-reviewedLast author
Circuit-level Simulation Methodology for Random Telegraph Noise by Using Verilog-AMS

Takuya Komawaki, Michitarou Yabuuchi, Ryo Kishida, Jun Furuta, Takashi Matsumoto, Kazutoshi Kobayashi

International Conference on IC Design and Technology, (I2) I2.01-04, May, 2017 Peer-reviewedLast author
Influence of Layout Structures to Soft Errors Caused by Higher-energy Particles on 28/65 nm FDSOI Flip-Flops

Masashi Hifumi, Haruki Maruoka, Shigehiro Umehara, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi

IEEE International Reliability Physics Symposium, SE5.1-SE5.4, Apr, 2017 Peer-reviewedLast author
A 16 nm FinFET Radiation-hardened Flip-Flop, Bistable Cross-coupled Dual-Modular-Redundancy FF for Terrestrial and Outer-Space Highly-reliable Systems

Kazutoshi Kobayashi, Jun Furuta, Haruki Maruoka, Masashi Hifumi, Shigetaka Kumashiro, Takashi Kato, Shumpei Kohri

IEEE International Reliability Physics Symposium, SE2.1-SE2.3, Apr, 2017 Peer-reviewedLead author
The Impact of RTN-Induced Temporal Performance Fluctuation Against Static Performance Variation

Takashi Matsumoto, Kazutoshi Kobayashi, Hidetoshi Onodera

Electron Devices Technology and Manufacturing, 31-32, Mar, 2017 Peer-reviewed
Degradation Caused by Negative Bias Temperature Instability Depending on Body Bias on NMOS or PMOS in 65 nm Bulk and Thin-BOX FDSOI Processes

Ryo Kishida, Kazutoshi Kobayashi

Electron Devices Technology and Manufacturing, 122-123, Mar, 2017 Peer-reviewedLast author
A Low Surge Voltage and Fast Speed Gate Driver for SiC MOSFET with Switched Capacitor Circuit

Mo Fei, Jun Furuta, Kazutoshi Kobayashi

Workshop on Wide Bandgap Power Devices and Applications, 282-285, Nov, 2016 Peer-reviewedLast author
Correlations between Plasma Induced Damage and Negative Bias Temperature Instability in 65 nm Bulk and Thin-BOX FDSOI Processes

Ryo Kishida, Kazutoshi Kobayashi

SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 25-27, Oct, 2016 Peer-reviewedLast author
A Radiation-hard Layout Structure to Control Back-Gate Biases in a 65 nm Thin-BOX FDSOI Process

Junki Yamaguchi, Jun Furuta, Kazutoshi Kobayashi

SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 28-30, Oct, 2016 Peer-reviewedLast author
Smart design environment for digital chips: Construction and deployment of design environment in which students can tapeout their chip designs

Kazutoshi Kobayashi

Journal of the Institute of Electronics, Information and Communication Engineers, 99(9) 891-894, Sep 1, 2016
Physical-Based RTN Modeling of Ring Oscillators in 40-nm SiON and 28-nm HKMG by Bimodal Defect-Centric Behaviors

Asusa Oshima, Takuya Komawaki, Kazutoshi Kobayashi, Ryo Kishida, Pieter Weckx, Ben Kaczer, Takashi Matsumoto, Hidetoshi Onodera

IEEE International Conference on Simulation of Semiconductor Processes and Devices, 327-330, Sep, 2016 Peer-reviewed
Size Optimization Technique for Logic Circuits that Considers BTI and Process Variations

Michitarou Yabuuchi, Kazutoshi Kobayashi

IPSJ Transactions on System LSI Design Methodology, 9 72-78, Aug, 2016 Peer-reviewedLast author
Analysis of Soft Error Rates in 65- and 28-nm FD-SOI Processes Depending on BOX Region Thickness and Body Bias by Monte-Carlo Based Simulations

Kuiyuan Zhang, Shigehiro Umehara, Junki Yamaguchi, Jun Furuta, Kazutoshi Kobayashi

IEEE Trans. on Nuclear Science, 63(4) 2002-2009, Aug, 2016 Peer-reviewedLast author
A Radiation-Hardened Non-Redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process

Jun Furuta, Junki Yamaguchi, Kazutoshi Kobayashi

IEEE Trans. on Nuclear Science, 63(4) 2080-2086, Aug, 2016 Peer-reviewedLast author
SOTB technology, which enables perpetually reliable CPU for IoT applications

Koichiro Ishibashi, Nobuyuki Sugii, Kazutoshi Kobayashi, Tomoaki Koide, Hiroki Nagatomi, Shiro Kamohara

2015 4th Berkeley Symposium on Energy Efficient Electronic Systems, E3S 2015 - Proceedings, Nov 24, 2015
Impact of Parasitic Inductors on Switching Operation of SiC MOSFET

2015(146) 101-106, Oct 29, 2015

Books and Other Publications

SystemVerilogによるFPGA/ディジタル回路設計入門

小林, 和淑, 寺澤, 真一, 吉河, 武文, 塩見, 準, 門本, 淳一郎

オーム社, Nov, 2023 (ISBN: 9784274231018)
ウェスト&ハリスCMOS VLSI回路設計

Weste, Neil H. E., Harris, David Money, 廣瀬, 哲也, 高橋, 篤司, 天野, 英晴, 山岡, 雅直, 高宮, 真, 宇佐美, 公良, 池田, 誠, 小林, 和淑, 戸川, 望, 小松, 聡, 平本, 俊郎, 佐藤, 高史, 石原, 亨, 黒川, 敦, 三堂, 哲寿

丸善出版, Jan, 2014 (ISBN: 9784621087213)
集積回路工学

吉本, 雅彦, 藤野, 毅, 松岡, 俊匡, 廣瀬, 哲也, 川口, 博, 小林, 和淑

オーム社, Sep, 2013 (ISBN: 9784274214271)
アナログ電子回路

永田, 真, 太田, 淳, 小林, 和淑, 廣瀬, 哲也, 松岡, 俊匡

オーム社, Mar, 2013 (ISBN: 9784274213441)
ディジタル集積回路の設計と試作

浅田, 邦博, 越智, 裕之, 池田, 誠, 小林, 和淑, 東京大学大規模集積システム設計教育研究センター

培風館, Jun, 2000 (ISBN: 4563035475)

Professional Memberships

Research Projects

高信頼性を要求される常時起動デバイスの特性変動の実測評価と動作レベルのモデル化

科学研究費助成事業, 基盤研究(C), 日本学術振興会, Apr, 2018 - Mar, 2023

松本高士, 西澤真一, 小林和淑
Intelligently controled device simulator utlizing small numer of dominant time constant approximation

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (C), Japan Society for the Promotion of Science, Apr, 2017 - Mar, 2021

Kumashiro Shigetaka
An IoT that can keep on running over years efficiently and reliably

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, Apr, 2015 - Mar, 2019

Kobayashi Kazutoshi, Stoffels Steve, Posthuma Niels, Li Xiangdong, Decoutere Stefaan
Integrated Circuit Design for Robust Operation under Low Supply Voltage

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 2010 - 2012

ONODERA Hidetoshi, TSUCHIYA Akira, KOBAYASHI Kazutoshi
Evaluation of Low-Cost Circuit-level Techniques to Compensate Temporal Errors.

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 2009 - 2011

KOBAYASHI Kazutoshi
Variation and Defect Aware Design of Integrated Circuits

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 2007 - 2009

ONODERA Hidetoshi, KOBAYASHI Kazutoshi, TSUCHIYA Akira
Fablication-friendly Configurable Processors in a nanometer LSI process

Grants-in-Aid for Scientific Research, Grant-in-Aid for Young Scientists (A), Japan Society for the Promotion of Science, 2006 - 2008

KOBAYASHI Kazutoshi
Research of a High-speed Signal Transmission Scheme for Integrated Circuits

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 2002 - 2004

ONODERA Hidetoshi, KOBAYASHI Kazutoshi, HASHIMOTO Masanori
ハードソフト同時設計によるシステムLSIの設計効率化・開発期間短期化

科学研究費助成事業, 若手研究(B), 日本学術振興会, 2002 - 2003

小林和淑
動き補償を利用した動画像の実時間背景・対象物分離アルゴリズムとハードウエアの開発

科学研究費助成事業, 特定領域研究, 日本学術振興会, 2001 - 2002

小野寺秀俊, 橋本昌宜, 小林和淑
設計者のための統合型VLSIテスト環境の開発

科学研究費助成事業, 奨励研究(A), 日本学術振興会, 2000 - 2001

小林和淑
Development of Statistical Performance Analysis and Optimization Methods for Large Scale Integrated Circuits

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 1999 - 2001

ONODERA Hidetoshi, KANBARA Hiroyuki, HASHIMOTO Masanori, KOBAYASHI Kazutoshi
Development of a Functional LSI Achieving Low-rate Multimedia Data Transmission.

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B)., Japan Society for the Promotion of Science, 1998 - 2000

ONODERA Hidetoshi, KOBAYASHI Kazutoshi
機能メモリ上でのベクトル量子化を用いた画像圧縮法の検討

科学研究費助成事業, 奨励研究(A), 日本学術振興会, 1998 - 1999

小林和淑
Development of a Memory-Based Low-Energy Processor for Real-Time Motion

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (C), Japan Society for the Promotion of Science, 1998 - 1999

MOSHNYAGA Vashily, TAMARU Keikichi, TSURUTA Naoyuki, SHUDO Kosho, KOBAYASHI Kazutoshi, ONODERA Hidetoshi
Optimization of detailed design for UDSM (ultra deep submicron) integrated circuits

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (C), Japan Society for the Promotion of Science, 1997 - 1998

ONODERA Hidetoshi, KOBAYASHI Kazutoshi, TAMARU Keikichi
Statistical modeling method for scaled MOSFET

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (A), Japan Society for the Promotion of Science, 1996 - 1997

ONODERA Hidetoshi, MATSUZAWA Akira, KOBAYASHI Kazutoshi, MOSHNYAGA Vasily, TAMURA Keikichi
Development of a Computing System by a Functional Memory Type Parallel Processor.

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (A), Japan Society for the Promotion of Science, 1995 - 1997

TAMARU Keikichi, YOSHIDA Toyohiko, KOBAYASHI Kazutoshi, VASILY Moshnyaga, ONODERA Hidetoshi
機能メモリ上でのベクトル量子化を用いた画像圧縮手法の検討

科学研究費助成事業, 奨励研究(A), 日本学術振興会, 1996 - 1996

小林和淑
演算機能を持つメモリLSIを用いたプロセッサボードの制御方式の検討

科学研究費助成事業, 奨励研究(A), 日本学術振興会, 1995 - 1995

小林和淑