| | Michihiro KoibuchiLast updated: 12/04/23 10:50 Academic Societies Technical Commitee, Cat.1: Network Applications and Big Data Processing, the 10th International Conference on Optical Internet (COIN2012)(1) , 3rd International Workshop on Advances in Networking and Computing (WANC), 2012(1) , Expert External Reviewer, the 48th Design Automation Conference (DAC)(1) , Member, IEEE and IEEE Computer Society(1) , Local Organization Committee, ASIAN'06 11th Annual Asian Computing Science Conference (2006)(1) , Technical Program Committee, International Conference on Embedded Software and Systems 2009, 2010,2011 (ICESS)(1) , Steering Committee Chairs, and Technical Program Cmmittee, International Symposium on Embedded Multicore Systems-on-Chip (MCSoC09), 2007, 2009, 2010 (IEEE CS press)(1) , Program Committee, 8th IEEE International Conference on Embedded Computing (EmbeddedCom-09) (Date: September 25-27, 2009. Location: Dalian, China)(1) , Technical Program Committee, System-Level Memory/Communication Design and Networks on Chip Track, Asia and South Pacific Design Automation Conference (ASP-DAC) 2010, 2011,2012(1) , International Conference on Networking and Computing, PC member, 2011, Nov (Hirosima)(1) , the 16th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC’10), Organizing Committee (Local Arrangement)(1) , The 16th International Conference on Parallel and Distributed Systems (ICPADS), Program Committee Member (Multicore Computing and Parallel/Distributed Architecture) 2010. Dec(Shanghai, China)(1) , IEEE Transactions on Computers, IEEE Transactions on Parallel and Distributed Systems, ACM Design Automation of Electronic Systems, 等の査読(1) Prizes 2012 Best Paper Candidate, Asia and South Pacific Design Automation Conference (ASP-DAC’12) 2011 Best Paper Award, International Conference on Networking and Computing(ICNC) Aug 2009 “Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network, 松谷 博士がIEEE Computer Society Japan Chapter Young Author Award 2009 Dec 2007 IEEE Computer Society Japan Chapter Young Author Award 2007, IEEE Computer Society Japan Chapter Misc An On/Off Link Regulations for Low-Power InfiniBand Jose Miguel Montanana, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano 情報処理学会研究報 告2009-ARC 184(21) Aug 2009 Performance and Cost Evaluations of On-Chip Network Topologies in FPGAs Sen In, Hiroki Matsutani, Daihan Wang, Michihiro Koibuchi, Hideharu Amano, IEICE Technical Reports, RECONF2009-3 109(26) 13-18 May 2009 A Link Removal Methodology for Application Specific Networks on chip on FPGAs Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano IEICE Technical Reports RECONF2008-7 108(48) 37-42 May 2008 A Temporal Correlation Based Port Combination Methodology for Application-Speci?c Networks-on-chip on FPGAs Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano 情報処理学会研究報告 2007-ARC(174) 133-138 Aug 2007 Overviewof SINET3 Next-generation Science InformationNetwork Shigeo Urushidani, Shunji Abe, Jun Matsukata,Yusheng Ji, KensukeFukuda, Michihiro Koibuchi, Shigeki Yamada Progresss in Informatics(NII) (4) 51-62 Mar 2007 A Parametric Study of Packet-Switched FPGA Overlay Networks Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano 電子情報通信学会技術研究報告 106(247, R) 31-36 Sep 2006 Bibliography 3D Integration for NoC-based SoC Architectures(Chapter 10: 3-D NoC on Inductive Wireless Interconnect pp.225-248) Hiroki Matsutani, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano, Abbas Sheibanyrad(編集), Frederic Petrot(編集), Axel Janstch(編集) Springer Nov 2010 |
Low Power Networks-on-Chip(Chapter 2: Run-Time Power-Gating Techniques for Low-Power On-Chip Networks pp.21-44) Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano, Cristina Silvano(編集) , Marcello Lajolo(編集), Gianluca Palermo(編集) Springer Oct 2010 |
Networks-on-chips: Theory and Practice Fayez Gebali (編集), Haytham Elmilgi (編集), Mohamed Watheq El-Kharashi (編集) , Michihiro Koibuchi, Hiroki Matsutani(Section 3) Crc Pr I Llc Mar 2009 ISBN:1420079786 |
Conferences Service-oriented Router that Shares and Searches Information Michihiro Koibuchi, Hiroaki Nishi 3rd EU-Japan Symposium on Future Internet and New Generation Networks Oct 2010 Future Ultra-Low-Power Computer Networks [Invited] Michihiro Koibuchi The 1st KOREA-CHINA-JAPAN Young Researchers Workshop May 2010 XNoTs: Crossbar-Connected Multi-Layer Topologies for 3-D NoCs Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano the IEEE International Symposium on Low-Power and High-Speed Chips (COOL Chips X) SINET3 for GRID Environment 鯉渕 道紘, 中尾 実, ネットワークグループ The Supercomputing (SC) conference, NAREGI Booth Papers A Case for Random Shortcut Topologies for HPC Interconnects Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova The 39th International Symposium on Computer Architecture (ISCA) Jun 2012 [Refereed] A Survey and Evaluation of Topology Agnostic Routing Algorithms J. Flich, T. Skeie, A.Mejia, O. Lysne, P. Lopez, A. Robles, J. Duato, M. Koibuchi, T. Rokicki, and J. C. Sancho IEEE Transactions on Parallel and Distributed Systems, 23(3) 405-425 Mar 2012 [Refereed] A Multi-Vdd Dynamic Variable-Pipeline On-Chip Router for CMPs Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano Proc. of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC’12) 407-412 Jan 2012 [Refereed] Performance Evaluation of Power-aware Multi-tree Ethernet for HPC Interconnects Michihiro Koibuchi, Takafumi Watanabe, Atsushi Minamihata, Masahiro Nakao, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano The Second International Conference on Networking and Computing (ICNC) 50-57 Dec 2011 [Refereed] A Dynamic Link-Width Optimization for Network-on-Chip Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano Proc. of the 1st International Workshop on Cyber- Physical Systems, Networks, and Applications (CPSNA’11) 106-108 Aug 2011 [Refereed] An Efficient Path Setup for a Hybrid Photonic Network-on-Chip Cisse Ahmadou Dit ADI, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga The International Journal of Networking and Computing 1(2) 244-259 Jul 2011 [Refereed] Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga IEEE Transactions on Computers, 60(6) 783-799 Jun 2011 [Refereed] A Vertical Bubble Flow Network using Inductive- Coupling for 3-D CMPs Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano Proc. of the 5th ACM/IEEE International Symposium on Networks-on-Chip (NOCS’11) 49-56 May 2011 [Refereed] Performance, Area, and Power Evaluations of Ultra Fine-Grained Run-Time Power-Gating Routers for CMPs Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano, IEEE Transactions on Computer-Aided Design of Integrated Circuits (TCAD) 30(4) 520-5333 Apr 2011 [Refereed] A Switch-tagged Routing Methodology for PC Clusters with VLAN Ethernet Michihiro Koibuchi, Tomohiro Otsuka, Tomohiro Kudoh, Hideharu Amano, IEEE Transactions on Parallel and Distributed System 22(2) 217-230 Feb 2011 [Refereed] An Analytical Network Performance Model for SIMD Processor CSX600 Interconnects Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano Journal of Systems Architecture 57 146-159 Jan 2011 [Refereed] A Variable-pipeline On-chip Router Optimized to Traffic Pattern Yuto Hirata, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano Proc. of the 3rd International Workshop on Network on Chip Architectures (NoCArc’10) 57-62 Dec 2010 [Refereed] An Efficient Path Setup for a Hybrid Photonic Network-on-Chip Cisse Ahmadou Dit ADI, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutumo Yoshinaga Proc. of the 2nd Workshop on Ultra Performance and Dependable Acceleration Systems (UPDAS’10) 156-161 Nov 2010 [Refereed] Semi-deflection Routing: A Non-minimal Fully-adaptive Routing for Virtual Cut-through Switching Network Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, International Journal of Computer and Network Security (IJCNS) 2(10) 52-58 Oct 2010 [Refereed] A Regular Expression Processor embedded in Service-friendly Router for Future Internet Yasutsugu Nagatomi, Michihiro Koibuchi, Hideyuki Kawashima, Koichi Inoue and Hiroaki Nishi 5th International Symposium on Embedded Multicore Systems-on-chip (MCSoC) Sep 2010 [Refereed] Dynamic Resource Allocation and QoS Control Capabilities of the Japanese Academic Backbone Network Shigeo Urushidani, Kensuke Fukuda, Michihiro Koibuchi, Motonori Nakamura, Shunji Abe, Yusheng Ji, Michihiro Aoki and Shigeki Yamada Future Internet 2(3) 295-307 Aug 2010 [Refereed] A Deadlock-free Non-minimal Fully Adaptive Routing using Virtual Cut-through Switching Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, 431-438 Jul 2010 [Refereed] Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks Jose Miguel Montanana, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, The 5th IEEE International Conference on Networking, Architecture, and Storage (NAS 2010) 218-227 Jul 2010 [Refereed] Hardware Architecture for Supporting High-speed Database Insertion on Service-oriented Router for Future Internet Tomoaki Makino, Michihiro Koibuchi, Hideyuki Kawashima, Koichi Inoue, Hiroaki Nishi Proc. of the 2010 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’10) 402-407 Jun 2010 [Refereed] Ultra Fine-Grained Run-Time Power Gating of On-Chip Routers for CMPs Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano Proc. of the 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS’10) 61-68 May 2010 [Refereed] A low-power fault-tolerant NoC using error correction and detection codes Yu Kojima, Hiroki Matsutani, Michihiro Koibuchi, and Hideharu Amano The IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN) 111-118 Feb 2010 [Refereed] Performance, Cost, and Power Evaluations of On-Chip Network Topologies in FPGAs Sen In, Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, and Hideharu Amano The IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN) 181-189 Feb 2010 [Refereed] Expansion of Bandwidth-on-Demand Capabilities in Japanese Academic Backbone Network Shigeo Urushidani, Kensuke Fukuda, Yusheng Ji, Shunji Abe, Michihiro Koibuchi, Motonori Nakamura, Shigeki Yamada, Michihiro Aoki IEEE BoD 2010 [Refereed] Efficient Scheduling Algorithms on Bandwidth Reservation Service of Internet using Genetic Algorithm Tomoyuki Hiroyasu, Kozo Kawasaki, Michihiro Koibuchi, Shigeo Urushidani, Mitsunori Miki and Masato Yoshimi The 9th International Conference on Intelligent Systems Design and Applications (ISDA), 683-688 Dec 2009 [Refereed] Evaluation of recovery methods for layer-1 bandwidth on demand service K. Shimizu, S. Urushidani, R. Hayashi, I. Inoue, K. Shiomoto, K. Fukuda, M. Koibuchi, S. Abe, Y. Ji, M. Nakamura, and S. Yamada ECOC2009 Sep 2009 [Refereed] Balanced Dimension- Order Routing for k-ary n-cubes Jose Miguel Montanana, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Proc. of the 4th International Symposium on Embedded Multicore Systems-on-Chip (MCSoC’09) CD-ROM Sep 2009 [Refereed] “Performance of Photonic Network on Chip using Prediction Switching Cisse Ahmadou Dit ADI，秋岡明香，吉永努，松谷宏紀，鯉渕道紘 情報処理学会研究報告2009-ARC-184 (31) Aug 2009 An On/Off Link Regulations for Low-Power InfiniBand Jose Miguel Montanana, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano 情報処理学会研究報 告2009-ARC-184 (21) Aug 2009 Performance Analysis of ClearSpeed’s CSX600 Interconnects Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Akihiro Shitara, Kenichi Miura, Hideharu Amano IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA) 203-210 Aug 2009 [Refereed] Fat HTree: A Cost-Efficient Tree-Based On-Chip Network Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, and Hideharu Amano, IEEE Transactions on Parallel and Distributed Systems 20(8) 1126-1141 Aug 2009 [Refereed] An On/Off Link Activation Method for Power Regulation in InfiniBand Jose Miguel Montanana, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano, Proc. of the 2009 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’09) 289-295 Jun 2009 [Refereed] Performance and Cost Evaluations of On-Chip Network Topologies in FPGAs Sen In, Hiroki Matsutani, Daihan Wang, Michihiro Koibuchi, Hideharu Amano IEICE Technical Reports RECONF2009 109(26) 13-18 May 2009 An On/Off Link Activation Method for Low-Power Ethernet in PC Clusters Michihiro Koibuchi, Tomohiro Otsuka, Hiroki Matsutani, Hideharu Amano, 22nd International Parallel and Distributed Processing Symposium (IPDPS) CD-ROM May 2009 [Refereed] Design of Versatile Academic Infrastructure for Multilyaer Network Services Shigeo Urushidani et al (計11 名、Michihiro Koibuchi は第5著者) IEEE Journal on Selected Areas in Communications (JSAC) 27(3) 253-267 Apr 2009 [Refereed] A Link Removal Methodology for Application-Specific Networks-on-chip on FPGAs Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano IEICE Transactions on Information and Systems E92-D(4) 575-583 Apr 2009 [Refereed] Prediction Router: Yet Another Low Latency On-Chip Router Architecture Hiroki Matsutani, Michihiro Koibuchi, and Hideharu Amano, Tsutomu Yoshinaga The 15th International Symposium on High-Performance Computer Architecture (HPCA) 367-378 Feb 2009 [Refereed] A Partially Network Reconfiguration Mechanism on Two dimensional Mesh and Torus with Faults Michihiro Koibuchi The IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN) 91-96 Feb 2009 [Refereed] Implementation and Evaluation of Layer-1 Bandwidth-on-Demand Capabilities in SINET3 Shigeo Urushidani, Kensuke Fukuda, Yusheng Ji, Michihiro Koibuchi, Shunji Abe, Motonori Nakamura, Shigeki Yamada, Kaori Shimizu, Rie Hayashi, Ichiro Inoue, Kohei Shiomoto, and Hiroyuki Tanuma IEEE International Conference on Communications (ICC) 1-6 2009 [Refereed] Impact of QoS Operations on an Experimental Testbed Network Jumpot Phuritatkul, Kien Nguyen, Michihiro Koibuchi, Yusheng Ji, Kensuke Fukuda, Shunji Abe, Jun Matsukata, Shigeo Urushidani, Shigeki Yamada, Simulation Modelling Practice and Theory 17(3) 528-537 Oct 2008 [Refereed] The Impact of Topology and Link Aggregation on PC Cluster with Ethernet Takafumi Watanabe, Masahiro Nakao, Tomoyuki Hiroyasu, Tomohiro Otsuka, Michihiro Koibuchi, IEEE International Conference on Cluster Computing (Cluster2008) 380-385 Sep 2008 [Refereed] A Link Removal Methodology for Network-on-Chip on Reconfigurable Systems Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano Proc. of the 18th International Conference on Field Programmable Logic and Applications (FPL'08) 269-274 Sep 2008 [Refereed] Semantic router using data stream to enrich services Koichi Inoue, Dai Akashi, Michihiro Koibuchi, Hideyuki Kawashima, Hiroaki Nishi International Conference on Future Internet Technologies (CFI08) 20-23 Jun 2008 [Refereed] Three-Dimensional Layout of On-Chip Tree-Based Networks Hiroki Matsutani, Michihiro Koibuchi, D.Frank Hsu, Hideharu Amano The 9th International Symposium on Parallel Architectures, Algorithms and Networks (I-SPAN) 281-288 May 2008 [Refereed] A Lightweight Fault-tolerant Mechanism for Network-on-chip Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy M. Pinkston Proc. of the 2nd ACM/IEEE International Symposium on Networks-on-Chip (NOCS’08) 13-22 Apr 2008 [Refereed] Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks Hiroki Matsutani, Michihiro Koibuchi, DaihanWang, Hideharu Amano Proc. of the 2nd ACM/IEEE International Symposium on Networks-on-Chip (NOCS’08) 23-32 Apr 2008 [Refereed] Resource Allocation and Provision for Bandwidth/Networks on Demand in SINET3 Shigeo Urushidani, Kensuke Fukuda, Yusheng Ji, Shunji Abe, Michihiro Koibuchi, Motonori Nakamura, Shigeki Yamada, Kaori Shimizu, Rie Hayashi, Ichiro Inoue, and Kohei Shiomoto, 2008 2nd IEEE International Workshop on Bandwidth on Demand (BoD 2008) 212-218 Apr 2008 [Refereed][Invited] Implementation of QoS Control Capabilities in SINET3 Shigeo Urushidani,Yusheng Ji, Jun Matsukata, KensukeFukuda, Shunji Abe, Michihiro Koibuchi, Shigeki Yamada 4th International Telecommunication Networking Workshop on QoS in Multiservice IP Networks (QoS-IP) 40-45 Feb 2008 [Refereed] Run-TimePower Gating of On-Chip Routers Using Look-Ahead Routing Hiroki Matsutani, Michihiro Koibuchi, DaihanWang, Hideharu Amano The 13th Asia and SouthPaci?c Design Automation Conference (ASP-DAC) 55-60 Jan 2008 [Refereed] Impact of Predictive Switching in 2-D Torus Networks Tsutomu Yoshinaga, Hirokazu Murakami, Michihiro Koibuchi International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA) 11-19 Dec 2007 [Refereed] A Port Combination Methodology for Application-Specific Networks-on-chip on FPGAs DaihanWang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano IEICE Transactions on Information and Systems (Special Section on Reconfigurable Systems) E90-D(12) 1914-1922 Dec 2007 [Refereed] |
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