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| | Tomohiro YonedaLast updated: 10/04/09 12:46 PapersA Floorplan Method for Asynchronous Circuits with Bundled-data Implementation on FPGAs Hiroshi Saito, Naohiro Hamada, Tomohiro Yoneda, and Takashi Nanya Proc. of 2010 IEEE International Symposium on Circuits and Systems May 2010 [Refereed] Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement H. Zheng, H. Yao, T. Yoneda IEEE Transactions on Computers 59(4) 561-573 Apr 2010 [Refereed] N-way Ring and Square Arbiters M. Imai, T. Yoneda, T. Nanya Proc. of ICCD 125-130 Oct 2009 [Refereed] Achieving degradation tolerance in a hardware accelerator with parallel functional units T. Yoneda, M Imai, H. Saito, A. Matsumoto Proc. of Third Workshop on Dependable and Secure Nanocomputing (WDSN 2009) 28-33 Jun 2009 [Refereed] Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous Designs H. Zheng, H. Yao, T. Yoneda Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 175-180 May 2009 [Refereed] MiscComarison of Standard Cell based Non-linear Asynchronous Pipelines Chammika Mannakkara, Tomohiro Yoneda IEICE Technical Report DC-2007(33) 49-54 Nov 2007 Synthesis of Timed Circuits based on Decomposition Tomohiro Yoneda and Chris Myers NII Technical Report (NII-20) Feb 2006 Synthesizing Timed Circuits from High Level Specification Languages Tomohiro Yoneda and Chris Myers NII Technical Report (NII-20) Feb 2003 Verifying Stacks and Queues Using Symbolic Simulation Techniques Y.Morihiro, T.Yoneda Proc. of 2000 International Workshop on RTL ATPG & DFT 119-128 Sep 2000 Implementing Fast QDI Boolean Function Blocks M.Saarepera, T.Yoneda IEICE Technical Report (FTS-99) 79-86 Oct 1999 Symbolic Verification of Statecharts J.Philipps, T.Yoneda IEICE Technical Report (FTS-95) 49-56 Jan 1995 ConferenceRecent Asynchronous Circuit Design Technologies [Invited] T. Yoneda SOIM-GCOE09 Nov 2009 |
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