| | Tomohiro YonedaLast updated: 12/04/16 16:41 Papers Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets Scott Little, David Walter, Chris Myers, Robert Thacker, Satish Batchu, Tomohiro Yoneda IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (to appear) 2011 [Refereed] Improving Dependability and Performance of Fully Asynchronous On-chip Networks Masashi IMAI, Tomohiro Yoneda Proc. of ASYNC 2011 (to appear) Apr 2011 [Refereed] Asynchronous Pipeline Controller Based on Early Acknowledgement Protocol Chammika Mannakkara , Tomohiro Yoneda IEICE Trans. E93-D(8) 2145-2191 Aug 2010 [Refereed] A Floorplan Method for Asynchronous Circuits with Bundled-data Implementation on FPGAs Hiroshi Saito, Naohiro Hamada, Tomohiro Yoneda, and Takashi Nanya Proc. of 2010 IEEE International Symposium on Circuits and Systems May 2010 [Refereed] Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement H. Zheng, H. Yao, T. Yoneda IEEE Transactions on Computers 59(4) 561-573 Apr 2010 [Refereed] N-way Ring and Square Arbiters M. Imai, T. Yoneda, T. Nanya Proc. of ICCD 125-130 Oct 2009 [Refereed] Achieving degradation tolerance in a hardware accelerator with parallel functional units T. Yoneda, M Imai, H. Saito, A. Matsumoto Proc. of Third Workshop on Dependable and Secure Nanocomputing (WDSN 2009) 28-33 Jun 2009 [Refereed] Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous Designs H. Zheng, H. Yao, T. Yoneda Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 175-180 May 2009 [Refereed] A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation (to appear) N. Hamada, Y. Shiga, T. Konishi, H. Saito, T. Yoneda, C. Myers, T. Nanya IPSJ Transactions on System LSI Design Methodology 2 64-79 Feb 2009 [Refereed] Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods D. Walter, S. Little, C. Myers, N. Seegmiller, T. Yoneda IEEE Trans. of Computer-Aided Design of Integrated Circuits and Systems 27(12) 2223-2235 Dec 2008 [Refereed] Misc An Online Routing Mechanism with Higher Fault-Tolerance for Network-on-Chip Daihan Wang, Chammika Mannakkara, Vijay Holimath, Tomohiro Yoneda 37-42 Oct 2011 Dynamic Link-Width Optimization for Network-on-Chip Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano CPSNA'11 poster session Aug 2011 A Case Study on Dependable Network-on-Chip Platform for Automotive Applications Chammika Mannakkara, Daihan WANG, Vijay HOLIMATH, Tomohiro YONEDA DC-2011(3) 11-16 Apr 2011 Comarison of Standard Cell based Non-linear Asynchronous Pipelines Chammika Mannakkara, Tomohiro Yoneda IEICE Technical Report DC-2007(33) 49-54 Nov 2007 Synthesis of Timed Circuits based on Decomposition Tomohiro Yoneda and Chris Myers NII Technical Report (NII-20) Feb 2006 Synthesizing Timed Circuits from High Level Specification Languages Tomohiro Yoneda and Chris Myers NII Technical Report (NII-20) Feb 2003 Verifying Stacks and Queues Using Symbolic Simulation Techniques Y.Morihiro, T.Yoneda Proc. of 2000 International Workshop on RTL ATPG & DFT 119-128 Sep 2000 Implementing Fast QDI Boolean Function Blocks M.Saarepera, T.Yoneda IEICE Technical Report (FTS-99) 79-86 Oct 1999 Symbolic Verification of Statecharts J.Philipps, T.Yoneda IEICE Technical Report (FTS-95) 49-56 Jan 1995 Conferences Recent Asynchronous Circuit Design Technologies [Invited] T. Yoneda SOIM-GCOE09 Nov 2009 |
|
|
|
|  |
