Ikeda Shoji

J-GLOBAL         Last updated: Oct 20, 2014 at 23:49
 
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Name
Ikeda Shoji
E-mail
s-ikedacies.tohoku.ac.jp
Affiliation
Tohoku University
Section
Center for Innovative Integrated Electronic Systems

Research Areas

 
 

Misc

 
OHNO Hideo, ENDOH Tetsuo, HANYU Takahiro, ANDO Yasuo, KASAI Naoki, IKEDA Shoji
The Journal of the Institute of Electronics, Information, and Communication Engineers   96(10) 771-775   Oct 2013
ENDOH Tetsuo, OHSAWA Takashi, KOIKE Hiroki, MIURA Sadahiko, HONJO Hiroaki, TOKUTOME Keiichi, IKEDA Shoji, HANYU Takahiro, OHNO Hideo
Technical report of IEICE. ICD   113(1) 27-32   Apr 2013
A 1Mb embedded memory was designed and fabricated using a cell consisting of four NFETs and two spin-transfer torque magnetic tunnel junctions (STT-MTJs) which is a nonvolatile memory device with excellent write endurance. A 32b fine-grained power...
MATSUNAGA Shoun, MIURA Sadahiko, HONJO Hiroaki, KINOSHITA Keizo, IKEDA Shoji, ENDOH Tetsuo, OHNO Hideo, HANYU Takahiro
Technical report of IEICE. ICD   113(1) 33-38   Apr 2013
Higher density and lower standby power are demanded in ternary content-addressable memory (TCAM), that realizes huge number of information retrieval at a time with its fully parallel manner. In this paper, we propose and demonstrate a four-MOS-tra...
SUZUKI Daisuke, NATSUI Masanori, IKEDA Shoji, HASEGAWA Haruhiro, MIURA Katsuya, HAYAKAWA Jun, ENDOH Tetsuo, OHNO Hideo, HANYU Takahiro
Technical report of IEICE. ICD   110(9) 47-52   Apr 2010
This paper presents a nonvolatile LUT (Lookup-Table) circuit in FPGA (Field-Programmable Gate Array) using a MTJ (Magnetic Tunnel Junction) device-based logic technology. To utilize a capability of MTJ devices, the combinational logic circuitry is...
TAKEMURA Riichiro, KAWAHARA Takayuki, MIURA Katsuya, YAMAMOTO Hiroyuki, HAYAKAWA Jun, MATSUZAKI Nozomu, ONO Kazuo, YAMANOUCHI Michihiko, ITO Kenchi, TAKAHASHI Hiromasa, IKEDA Shoji, HASEGAWA Haruhiro, MATSUOKA Hideyuki, OHNO Hideo
Technical report of IEICE. ICD   110(9) 53-57   Apr 2010
A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ns at a supply voltage of 1.8 V. The chip was fabricated with 150-nm CMOS and a 100×200 nm^2 tunnel magnetoresistive device ele...