Naoya Onizawa

Profile Information

Affiliation: Associate Professor (Distinguished Researcher), Research Institute of Electrical Communication, Tohoku University

Degree: Ph.D. in Engineering(Mar, 2009, Tohoku University)

J-GLOBAL ID: 201401089778586753
researchmap Member ID: 7000006886

Research Interests

Research Areas

Research History

Jan, 2021 - Present

育成対象者, 文部科学省「世界で活躍できる研究者戦略育成事業・学際融合グローバル研究者育成東北イニシアティブ」
Nov, 2020 - Present

Associate Professor, Research Institute of Electrical Communication, Tohoku University
May, 2020 - Present

(Distinguished Researcher), Tohoku University
Oct, 2018 - Mar, 2022

PRESTO researcher, JST
Dec, 2018 - Oct, 2020

Assistant Professor, Research Institute of Electrical Communication, Tohoku University
Dec, 2013 - Nov, 2018

Assistant Professor, Frontier Research Institute for Interdisciplinary Sciences, Tohoku University
Jun, 2015

Guest associate professor, University of Southern Brittany
Oct, 2013 - Nov, 2013

Research Institute of Electrical Communication, Tohoku University
Apr, 2012 - Sep, 2013

Postdoc fellow, Department of Electrical and Computer Engineering, McGill University
Oct, 2011 - Mar, 2012

Postdoc fellow, Department of Electrical and Computer Engineering, University of Waterloo
Apr, 2011 - Sep, 2011

Postdoc fellow, Department of Electrical and Computer Engineering, McGill University

Committee Memberships

Jun, 2020 - Present

英文論文誌A編集委員, 電子情報通信学会
Jun, 2020 - Present

和文論文誌A編集委員, 電子情報通信学会
Jan, 2022 - Dec, 2022

Guest Editor for special issue of Nanoarch 2021, IEEE Transactions on Nanotechnology
Apr, 2021 - Oct, 2021

Program Co-Chair, 16th ACM/IEEE International Symposium on Nanoscale Architectures
Oct, 2020 - May, 2021

Program Co-Chair, 2021 IEEE International Symposium on Multiple-Valued Logic
Sep, 2018 - May, 2021

Technical Program Committee, IEEE International Symposium on Asynchronous Circuits and Systems
Sep, 2016 - May, 2021

Technical Program Committee, IEEE International Symposium on Multiple-Valued Logic
Jan, 2017 - Dec, 2019

Members-at-Large, Technical Committee on Multiple-Valued Logic of IEEE Computer Society
Sep, 2017 - May, 2019

Publication chair, 2019 IEEE International Symposium on Asynchronous Circuits and Systems
Sep, 2014 - May, 2016

Secretary, 2016 IEEE International Symposium on Multiple Valued Logic

Awards

Dec, 2022

第16回青葉工学振興会賞, 確率的コンピューティングに基づく脳型情報処理, 一般財団法人青葉工学振興会

鬼沢直哉
Apr, 2020

令和2年度科学技術分野の文部科学大臣表彰・若手科学者賞, 確率的コンピューティングに基づく脳型情報処理システム研究, 文部科学省

鬼沢直哉
Mar, 2018

平成29年度電気・情報系若手優秀研究賞, 東北大学電気・情報系研究教授会

鬼沢直哉
May, 2016

Kenneth C. Smith Early Career Award for Microelectronics Research in 46th IEEE International Symposium on Multiple-Valued Logic (ISMVL), IEEE Technical Committee on Multiple-Valued Logic

Naoya Onizawa
Dec, 2014

一般財団法人青葉工学振興会第20回青葉工学研究奨励賞, 非同期式信号処理に基づく高速・低電力VLSIの実現に関する研究, 一般財団法人青葉工学振興会

鬼沢直哉
Aug, 2014

3rd place at Falling Walls Lab Sendai 2014, Paradigm Shift in Computing, Falling Walls Lab

Naoya Onizawa
May, 2014

Best Paper Finalist (2014 IEEE International Symposium on Asynchronous Circuits and Systems), IEEE

N. Onizawa, S. Matsunaga, T. Hanyu
Jul, 2010

Best Paper Award (2010 IEEE Computer Society Annual Symposium on VLSI), IEEE

N. Onizawa, T. Funazaki, A. Matsumoto, T. Hanyu
Dec, 2004

学生優秀論文賞受賞(平成１６年度電子情報通信学会東北支部), 電子情報通信学会

Papers

135

Enhanced convergence in p-bit based simulated annealing with partial deactivation for large-scale combinatorial optimization problems

Naoya Onizawa, Takahiro Hanyu

Scientific Reports, 14(1) 1339, Jan 16, 2024 Peer-reviewedLead authorCorresponding author
Stochastic Implementation of Simulated Quantum Annealing on PYNQ

Taiga Kubuta, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

2023 International Conference on Field Programmable Technology (ICFPT), Dec 12, 2023
Improving Stochastic Quantum-Like Annealing Based on Rerandomization

Ryoma Sasaki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec 4, 2023 Peer-reviewed
Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing

Naoya Onizawa, Kota Katsuki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu

IEEE Transactions on Neural Networks and Learning Systems, 34(12) 10999-11005, Dec, 2023 Lead authorCorresponding author
Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing

Naoya Onizawa, Kyo Kuroki, Duckgyu Shin, Takahiro Hanyu

IEEE Open Journal of Signal Processing, 4 452-461, Nov, 2023 Peer-reviewedLead authorCorresponding author
Self-Adaptive Gate Control for Efficient Escape From Local Minimum Energy on Invertible Logic

Naoya Onizawa, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu

IEEE Access, 11 44923-44931, May, 2023 Peer-reviewedLead authorCorresponding author
Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing

Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu

IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 13(1) 108-118, Mar, 2023 Peer-reviewed
Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing

Kota Katsuki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Oct 24, 2022 Peer-reviewed
Implementation of CMOS Invertible Logic on Zynq-SoC Platform: A Case Study of Training BNN

D. Shin, N. Onizawa, T. Hanyu

Journal of Applied Logics, 9(3) 585-606, Jun, 2022 Peer-reviewed
CMOS Invertible Logic: Bidirectional operation based on the probabilistic device model and stochastic computing

Naoya Onizawa, Takahiro Hanyu

IEEE Nanotechnology Magazine, 16(1) 33-46, Feb, 2022 Peer-reviewedInvitedLead authorCorresponding author
Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices

Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu

2021 IEEE Workshop on Signal Processing Systems (SiPS), Oct, 2021 Peer-reviewedLead authorCorresponding author
Design Automation of Invertible Logic Circuit From a Standard HDL Description

M. Kato, N. Onizawa, T. Hanyu

Journal of Applied Logics, 8(5) 1311-1333, Jun, 2021 Peer-reviewed
High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians

Naoya Onizawa, Takahiro Hanyu

2021 IEEE International Symposium on Circuits and Systems (ISCAS), May, 2021 Peer-reviewedLead authorCorresponding author
A Design Framework for Invertible Logic

Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 40(4) 655-665, Apr, 2021 Peer-reviewedLead authorCorresponding author
Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices

Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu

IEEE Open Journal of Circuits and Systems, 2 782-791, 2021 Peer-reviewedLead authorCorresponding author
Sparse Random Signals for Fast Convergence on Invertible Logic

Naoya Onizawa, Makoto Kato, Hitoshi Yamagata, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu

IEEE Access, 9 62890-62898, 2021 Peer-reviewedLead authorCorresponding author
Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN

Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu

IEEE Transactions on Circuits and Systems I: Regular Papers, 68(1) 67-76, Jan, 2021 Peer-reviewed
Memristive Computational Memory Using Memristor Overwrite Logic (MOL)

Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah, Naoya Onizawa, Takahiro Hanyu

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(11) 2370-2382, Nov, 2020 Peer-reviewed
Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic

Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu

IEEE Access, 8 188004-188014, Oct, 2020 Peer-reviewed
High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter

Naoya Onizawa, Shogo Mukaida, Akira Tamakoshi, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(10) 2171-2181, Oct, 2020 Peer-reviewedLead authorCorresponding author

Misc.

CMOSインバーティブルロジック［Ⅲ・完］――ハードウェア実現と応用例――

鬼沢直哉

電子情報通信学会学会誌, 106(1) 58-65, Jan, 2023 InvitedLead author
CMOSインバーティブルロジック［Ⅱ］――設計手法とツール――

鬼沢直哉

電子情報通信学会学会誌, 105(12) 1458-1465, Dec, 2022 InvitedLead author
CMOSインバーティブルロジック［I］――確率的双方向計算手法の基礎――

鬼沢直哉

電子情報通信学会学会誌, 105(10) 1241-1247, Oct, 2022 InvitedLead author
Energy-efficient brainware LSI based on stochastic computing

N. Onizawa, K. Matsumiya, T. Hanyu

IEICE Fundamental Review, 11(1) 28-39, Jul, 2017 Invited
Stochastic Computation for Energy-Efficient Brainware LSI

30 202-207, May 11, 2017
Measurement of Magnitude Response of FIR Filters Based on Stochastic Computation

30 38-40, May 11, 2017
On Measurement Methods of Frequency Magnitude Responses for Digital Filters Based on Stochastic Computation

2017(19) 1-6, Mar 13, 2017
視覚的注意計算モデルのハードウェア実装に向けた基礎的考察

西野海斗, 鬼沢直哉, 松宮一道, 塩入論, 羽生貴弘

電気関係学会東北支部連合大会講演論文集(CD-ROM), 2017, 2017
Hardware Implementation of Stochastic Gammatone Filter

116(95) 29-34, Jun 16, 2016
Design of a Stochastic Gabor Filter for Highly Parallel Feature-Extraction Hardware

115(318) 35-40, Nov 20, 2015
C-12-27 Design of an MTJ-Based True Random Number Generator with Probability-Variation Suppressing

Oosawa Satoshi, Konishi Takayuki, Onizawa Naoya, Hanyu Takahiro

Proceedings of the IEICE General Conference, 2015(2) 88-88, Feb 24, 2015
Nonvolatile Logic-in-Memory Architecture and Its Application to Low-Power VLSI Systems

羽生貴弘, 羽生貴弘, 羽生貴弘, 鈴木大輔, 鈴木大輔, 望月明, 望月明, 夏井雅典, 夏井雅典, 夏井雅典 …

電子情報通信学会技術研究報告, 115(6(ICD2015 1-15)), 2015
Fault-Tolerant Logical Integrated Circuits Based on Stochastic Computation

KATAGIRI Daisaku, ONIZAWA Naoya, HANYU Takahiro

IEICE technical report. Dependable computing, 114(22) 27-31, Apr 25, 2014
Low-Power IP Lookup LSI Based on Sparse Clustered Networks

ONIZAWA Naoya, GROSS Warren, HANYU Takahiro

IEICE technical report. Circuits and systems, 113(463) 193-198, Mar 6, 2014
Controller-Sharing Based Asynchronous Power-Gating Scheme and Its Application

KAWANO Takao, ONIZAWA Naoya, Matsumoto Atsushi, HANYU Takahiro

Technical report of IEICE. VLD, 111(324) 215-220, Nov 28, 2011
Controller-Sharing Based Asynchronous Power-Gating Scheme and Its Application

KAWANO Takao, ONIZAWA Naoya, Matsumoto Atsushi, HANYU Takahiro

IEICE technical report. Dependable computing, 111(325) 215-220, Nov 28, 2011
Fault-Detectable 2-Color Code for Asynchronous Bidirectional Communication Links

MATSUMOTO Atsushi, ONIZAWA Naoya, HANYU Takahiro

IEICE technical report. Dependable computing, 111(325) 37-42, Nov 28, 2011
Controller-Sharing Based Asynchronous Power-Gating Scheme and Its Application

2011(38) 1-6, Nov 21, 2011
C-12-10 非同期式チップ間リンク速度の定量的評価手法(センサ・有線通信,C-12.集積回路,一般セッション)

鬼沢直哉, 羽生貴弘

電子情報通信学会ソサイエティ大会講演論文集, 2010(2) 71-71, Aug 31, 2010
C-007 Asynchronous Communication Scheme based on Multiple-valued 1-color Encoding and Its Application toward Network-on-Chip

Matsumoto Atsushi, Onizawa Naoya, Hanyu Takahiro

9(1) 385-386, Aug 20, 2010

Books and Other Publications

Design and Applications of Emerging Computer Systems

Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu (Role: Contributor, Chapter of Stochastic Computing: Applications of Ising Models Based on Stochastic Computing)

Springer, Jan, 2024 (ISBN: 9783031424779)
Stochastic Computing: Techniques and Applications,

N. Onizawa, W. J. Gross, T. Hanyu (Role: Contributor, Chapter 9 (Brain-Inspired Computing))

Springer, Feb, 2019 (ISBN: 9783030037291)
百花繚覧 vol. 1

鬼沢直哉 (Role: Contributor, 第５章(人間的（脳型）コンピューティングによる安全で快適な暮らしの実現に向けて))

東北大学出版, Jan, 2019 (ISBN: 9784861633133)
VLSI 2010 Annual Symposium

N. Onizawa, T. Funazaki, A. Matsumoto, T. Hanyu (Role: Contributor, Chapter 2)

Springer, 2012 (ISBN: 9789400714885)

Presentations

Brainware Information Processing Based on Stochastic Computing

Naoya Onizawa

Conference, IMT Atlantique, Nov, 2022 Invited
Fast-Conversing Simulated Annealing of Ising Models Based on Integral Stochastic Computing

Naoya Onizawa

Edge Intelligence Workshop 2022,, Sep 20, 2022 Invited
最適化問題が実現する幸せな未来社会：量子と古典コンピューターの共創「古典コンピューターによる最適化問題」

鬼沢直哉

第14回実践データ駆動科学オンラインセミナー, Sep 2, 2022 Invited
大規模 SC-SA 法の高速求解向け FPGA 実装と評価

口分田大芽, シントッキュ, 鬼沢直哉, 羽生貴弘

2022 年度電気関係学会東北支部連合大会, Sep, 2022
Stochastic演算に基づくQMCによるアニーリング処理の高速化

佐々木遼真, 鬼沢直哉, 羽生貴弘

2022年度電気関係学会東北支部連合講演論文集, Aug, 2022
Integral Stochastic演算に基づくSimulated Annealing法の高速化

勝木康太, シントッキュ, 鬼沢直哉, 羽生貴弘

2021年度電気関係学会東北支部連合大会講演論文集, Aug 26, 2021
In-Hardware Training Chip Based on CMOS Invertible Logic

N. Onizawa

The 7th International Symposium on Brainware LSI, Mar 31, 2021
CMOSインバーティブルロジックとその学習ハードウェアへの応用展開

鬼沢直哉

第42回IBISML研究会, Mar 2, 2021 Invited
大規模CMOSインバーティブルロジック回路実現向け設計自動化ツールの構築

加藤諒, 鬼沢直哉, 羽生貴弘

信学会第2種研究会「多値論理とその応用」, Jan 9, 2021
大規模インバーティブルロジック回路実現へ向けた設計自動化手法

加藤諒, 鬼沢直哉, 羽生貴弘

2020年度電気関係学会東北支部連合大会, Aug 27, 2020
Stochastic Computing for Brainware LSI

N. Onizawa

2019 International Workshop on Emerging Technologies for Brainwrae LSI and Its Applications, Dec 13, 2019 Invited
Probabilistic learning algorithm based on CMOS invertible logic

Nov, 2019
Design of MTJ-based true random number generator

Sep, 2019
High-speed learning hardware based on CMOS invertible logic

Aug, 2019
Multi-context TCAM for approximate computing

2019年度電気関係学会東北支部連合大会, Aug, 2019
Stochastic Computing for Brainwrae LSI

N. Onizawa, W. J. Gross, T. Hanyu

26th IEEE International Symposium on Asynchronous Circuits and Systems, Special Session, May 12, 2019 Invited
Stochastic Computing for Brainware LSI

N. Onizawa, S. Koshita, S. Sakamoto, M. Kawamata, T. Hanyu, W. J. Gross, T. Hanyu

The 2019 RIKEN International Workshop on Neuromorphic Computing, Mar 11, 2019 Invited
Efficient CMOS Invertible Logic Using Stochastic Computing

N. Onizawa, S. C. Smithson, B. H. Meyer, W. J. Gross, T. Hanyu Naoya

The 6th International Symposium on Brainware LSI, Mar 2, 2019
Energy-Efficient Brainwave LSI Based on Stochastic Computation

ONIZAWA Naoya

Sep 14, 2018 Invited
ストカスティック演算に基づくインバーティブルロジック回路の構成

西野海斗, 鬼沢直哉, 羽生貴弘

2018年電子情報通信学会ソサイエティ大会, Sep 12, 2018

Professional Memberships

IEICE
IEEE

Research Projects

Development of Quantum Monte-Carlo Hardware Based on Probabilistic Device Model

Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B), Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, Apr, 2021 - Mar, 2025
Study of Invertible logic for edge-type learning hardware

Basic Research Programs (Precursory Research for Embryonic Science and Technology :PRESTO), PRESTO, JST, Oct, 2018 - Mar, 2022

ONIZAWA Naoya
Development of Dark Silicon Logic LSI for Brainware Computing

Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (S), Grant-in-Aid for Scientific Research (S), Japan Society for the Promotion of Science, May, 2016 - Mar, 2021
Brainware Large-Scale Vision Hardware Based on Parallel Stochastic Computing

Grants-in-Aid for Scientific Research Grant-in-Aid for Challenging Exploratory Research, Grant-in-Aid for Challenging Exploratory Research, Japan Society for the Promotion of Science, Apr, 2016 - Mar, 2019

ONIZAWA Naoya
Design of Ultra-Low Power IP-Packet-Processing LSI Based on Probabilistic Computing

Grants-in-Aid for Scientific Research Grant-in-Aid for Young Scientists (A), Grant-in-Aid for Young Scientists (A), Japan Society for the Promotion of Science, Apr, 2014 - Mar, 2018

Onizawa Naoya
脳型コンピューティング向けダーク・シリコンロジックLSIの基盤技術開発

科学研究費助成事業, 基盤研究(A), 日本学術振興会, Apr, 2016 - Mar, 2017

羽生貴弘, 米田友洋, 今井雅, 鬼沢直哉

Industrial Property Rights

特開2017-123134 半導体装置

羽生貴弘, 望月明, 鬼沢直哉, 玉越晃, 大野英男
特開2016-225000 記憶装置

羽生貴弘, 鬼沢直哉, 大野英男
特許第5998381号半導体記憶装置

羽生貴弘, 松永翔雲, 鬼沢直哉, ガウデット,ヴィンセント
特許第5935105号非同期プロトコル変換装置

羽生貴弘, 鬼沢直哉
特開2013-235620 半導体記憶装置及びその駆動方法

羽生貴弘, 松永翔雲, 鬼沢直哉, ガウデット,ヴィンセント
特開2012-191531 非同期データ転送装置

羽生貴弘, 鬼沢直哉, 松本敦
WO2011-149066 非同期プロトコル変換装置

羽生貴弘, 鬼沢直哉

Profile Information

Research Interests

Research Areas

Research History

Committee Memberships

Awards

Papers

Misc.

Books and Other Publications

Presentations

Professional Memberships

Research Projects

Industrial Property Rights

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