Takashi Sato

J-GLOBAL         Last updated: Aug 31, 2019 at 12:50
 
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Name
Takashi Sato
URL
http://easter.kuee.kyoto-u.ac.jp/
Affiliation
Kyoto University
Section
Graduate School of Informatics
ORCID ID
0000-0002-1577-8259

Published Papers

 
C. Cook, H. Zhao, T. Sato, M. Hiromoto, and S. Tan
Integration, the VLSI Journal   Vol(No)    Dec 2019   [Refereed]
S. Bian, M. Hiromoto, and T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E102-A(2) 430-439   Feb 2019   [Refereed]
Y. Ogasahara, K. Kuribara, M. Shintani, and T. Sato
Japanese Journal of Applied Physics (JJAP)   58(SB) SBBG03-SBBG03   Jan 2019   [Refereed]
M. Shintani, Y. Nakamura, K. Oishi, M. Hiromoto, T. Hikihara, and T. Sato
IEEE Transactions on Power Electronics (TPEL)   33(12) 10774-10783   Dec 2018   [Refereed]
M. Hiromoto, M. Yoshinaga, and T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E101-A(7) 1035-1044   Jul 2018   [Refereed]
S. Yamamori, M. Hiromoto, and T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E101-A(7) 1092-1100   Jul 2018   [Refereed]
R. Zhou, M. Shintani, M. Hiromoto, and T. Sato
Nonlinear Theory and Its Applications, IEICE   9(3) 344-357   Jul 2018   [Refereed]
Y. Tanaka, S. Bian, M. Hiromoto, and T. Sato
IEEE Transactions on Circuits and Systems--II: Express Briefs (TCASII)   65(5) 602-606   May 2018   [Refereed]
M. Shintani, Z. Qin, K. Kuribara, Y. Ogasahara, M. Hiromoto, and T. Sato
Japanese Journal of Applied Physics (JJAP)   57(4S) 04FL05-04FL05   Mar 2018   [Refereed]
H. Gyoten, M. Hiromoto, and T. Sato
IEICE Transactions on Information and Systems   E101-D(2) 314-323   Feb 2018   [Refereed]
Y. Fujita, M. Hiromoto, and T. Sato
IEEE Transactions on Bio-Medical Engineering   65(1) 189-198   Jan 2018   [Refereed]
S. Bian, S. Morita, M. Shintani, H. Awano, M. Hiromoto, and T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E100-A(12) 2797-2806   Dec 2017   [Refereed]
H. Awano and T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E100-A(12) 2807-2815   Dec 2017   [Refereed]
A. Mohanty, K. Sutaria, H. Awano, T. Sato, and Y. Cao
IEEE Transactions on Very Large Scale Integration (VLSI) Systems   25(8) 2248-2257   Aug 2017   [Refereed]
S. Morita, S. Bian, M. Shintani, M. Hiromoto, and T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E100-A(7) 1464-1472   Jul 2017   [Refereed]
H. Awano, S. Morita, and T. Sato
IEEE Transactions on Very Large Scale Integration (VLSI) Systems   25(4) 1455-1466   Apr 2017   [Refereed]
M. Shintani, Y. Nakamura, M. Hiromoto, T. Hikihara, and T. Sato
Japanese Journal of Applied Physics (JJAP)   56(4S) 04CR07-04CR07   Mar 2017   [Refereed]
M. Shintani, T. Uezono, K. Hatayama, K. Masu, and T. Sato
Journal of Electronic Testing: Theory and Applications (JETTA)   32(5) 601-609   Oct 2016   [Refereed]
H. Awano, M. Hiromoto, and T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E99-A(7) 1390-1399   Jul 2016   [Refereed]
S. Bian, M. Shintani, M. Hiromoto, and T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E99-A(7) 1400-1409   Jul 2016   [Refereed]
T. Imagawa, M. Hiromoto, H. Ochi, and T. Sato
IEICE Transactions on Electronics   E98-C(7) 741-750   Jul 2015   [Refereed]
H. Shimizu, H. Awano, M. Hiromoto, and T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E97-A(12) 2383-2392   Dec 2014   [Refereed]
H. Awano, M. Hiromoto, and T. Sato
IEEE Transactions on Device and Materials Reliability   14(3) 833-843   Sep 2014   [Refereed]
M. Shintani and T. Sato
IEICE Transactions on Information and Systems   E97-D(8) 2095-2104   Aug 2014   [Refereed]
M. Shintani, T. Uezono, T. Takahashi, K. Hatayama, T. Aikyo, K. Masu, and T. Sato
IEEE Transactions on Computer-Aided Design   33(7) 1056-1066   Jul 2014   [Refereed]
K. B. Sutaria, J. B. Velamala, C. Kim, T. Sato, and Y. Cao
IEEE Transactions on Device and Materials Reliability   14(2) 607-615   Jun 2014   [Refereed]
S. Hagiwara, T. Date, K. Masu, and T. Sato
IEICE Transactions on Electronics   E97-C(4) 280-288   Apr 2014   [Refereed]
K. Yamanaga, R. Takahashi, S. Hagiwara, K. Masu, and T. Sato
IEICE Transactions on Electronics   E97-C(1) 77-84   Jan 2014   [Refereed]
J. B. Velamala, K. B. Sutaria, H. Shimizu, H. Awano, T. Sato, G. Wirth, and Y. Cao
IEEE Transactions on Electron Devices   60(11) 3645-3654   Nov 2013   [Refereed]
T. Imagawa, H. Tsutsui, H. Ochi, and T. Sato
IEICE Transactions on Electronics   E96-C(4) 454-462   Apr 2013   [Refereed]
H. Yuasa, H. Tsutsui, H. Ochi, and T. Sato
IEICE Transactions on Electronics   E96-C(4) 473-481   Apr 2013   [Refereed]
M. Shintani and T. Sato
IEICE Transactions on Information and Systems   E96-D(2) 303-313   Feb 2013   [Refereed]
J. Kawashima, H. Tsutsui, H. Ochi, and T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E95-A(12) 2242-2250   Dec 2012   [Refereed]
T. Enami, T. Sato, and M. Hashimoto
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E95-A(12) 2261-2271   Dec 2012   [Refereed]
H. Awano, H. Tsutsui, H. Ochi, and T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E95-A(12) 2272-2283   Dec 2012   [Refereed]
S. Hagiwara, K. Yamanaga, R. Takahashi, K. Masu, and T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E93-A(12) 2409-2416   Dec 2010   [Refereed]
T. Imagawa, M. Hiromoto, H. Ochi, and T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E93-A(12) 2524-2532   Dec 2010   [Refereed]
K. Yamanaga, S. Amakawa, K. Masu, and T. Sato
IEICE Transactions on Electronics   E93-C(3) 347-354   Apr 2010   [Refereed]
T. Uezono, K. Masu, and T. Sato
IEICE Transactions on Electronics   E93-C(3) 324-331   Mar 2010   [Refereed]
T. Kanamoto, T. Okumura, K. Furukawa, H. Takafuji, A. Kurokawa, K. Hachiya, T. Sakata, M. Tanaka, H. Nakashima, H. Masuda, T. Sato, and M. Hashimoto
IEICE Transactions on Electronics   E93-C(3) 388-392   Mar 2010   [Refereed]
Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, and Y. Inoue
IEEE Transactions on Computer-Aided Design   29(2) 250-260   Feb 2010   [Refereed]
T. Sakata, T. Okumura, A. Kurokawa, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto, K. Hachiya, K. Furukawa, M. Tanaka, H. Takafuji, and T. Kanamoto
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E92-A(12) 3016-3023   Dec 2009   [Refereed]
T. Sato, H. Ueyama, N. Nakayama, and K. Masu
IEEE Journal of Solid-State Circuits   44(11) 2977-2986   Nov 2009   [Refereed]
A. Kurokawa, T. Sato, T. Kanamoto, and M. Hashimoto
IEEE Transactions on Electron Devices   56(9) 1840-1851   Sep 2009   [Refereed][Invited]
K. Masu, N. Ishihara, N. Nakayama, T. Sato, and S. Amakawa
IEICE Electronics Express (ELEX)   6(11) 703-720   Jun 2009   [Refereed][Invited]
K. Yamanaga, T. Sato, and K. Masu
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E92-A(4) 976-982   Apr 2009   [Refereed]
T. Okumura, A. Kurokawa, H. Masuda, T. Kanamoto, M. Hashimoto, H. Takafuji, H. Nakashima, N. Ono, T. Sakata, and T. Sato
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E92-A(4) 990-997   Apr 2009   [Refereed]
T. Uezono, T. Sato, and K. Masu
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E92-A(4) 1024-1030   Apr 2009   [Refereed]
S. Hagiwara, T. Sato, and K. Masu
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E92-A(4) 1031-1038   Apr 2009   [Refereed]
K. Yamada, T. Sato, N. Nakayama, S. Amakawa, K. Masu, and S. Kumashiro
IEICE Transactions on Electronics   E91-C(7) 1142-1150   Jul 2008   [Refereed]
M. Imai, T. Sato, N. Nakayama, and K. Masu
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E91-A(4) 957-964   Apr 2008   [Refereed]
S. Hagiwara, T. Uezono, T. Sato, and K. Masu
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E91-A(4) 951-956   Apr 2008   [Refereed]
M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera
IEICE Transactions on Information and Systems   E91-D(3) 655-660   Mar 2008   [Refereed]
Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye
IEEE Transactions on Circuits and Systems--II: Express Briefs (TCASII)   54(10) 868-872   Oct 2007   [Refereed]
H. Kobayashi, N. Ono, T. Sato, J. Iwai, H. Nakashima, T. Okumura, and M. Hashimoto
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E90-A(4) 808-814   Apr 2007   [Refereed]
T. Sato, J. Ichimiya, N. Ono, and M. Hashimoto
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E89-A(12) 3491-3499   Dec 2006   [Refereed]
K. Hachiya, H. Kobayashi, T. Okumura, T. Sato, and H. Oka
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E89-A(4) 865-872   Apr 2006   [Refereed]
T. Sato, M. Hashimoto, and H. Onodera
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E88-A(12) 3429-3436   Dec 2005   [Refereed]
T. Sato, J. Ichimiya, N. Ono, K. Hachiya, and M. Hashimoto
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E88-A(12) 3382-3389   Dec 2005   [Refereed]
T. Sato and H. Masuda
Journal of Analog Integrated Circuits and Signal Processing   42(3) 209-217   Mar 2005   [Refereed]
K. Takeuchi, K. Yanagisawa, T. Sato, K. Sakamoto, and S. Hojo
IEEE Transactions on Computer-Aided Design   23(9) 1377-1383   Sep 2004   [Refereed]
A. Kurokawa, T. Sato, and H. Masuda
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E86-A(12) 2933-2941   Dec 2003   [Refereed]
Y. Cao, M. Orshansky, T. Sato, D. Sylvester, and C. Hu
IEEE Circuits and Devices Magazine   19(4) 17-23   Jul 2003   [Refereed]
T. Sato, Y. Cao, K. Agarwal, D. Sylvester, and C. Hu
IEEE Transactions on Computer-Aided Design   22(5) 560-572   May 2003   [Refereed]
A. Kurokawa, K. Hachiya, T. Sato, K. Tokumasu, and H. Masuda
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E86-A(4) 841-845   Apr 2003   [Refereed]
T. Sato, D. Sylvester, Y. Cao, and C. Hu
IEEE Journal of Solid-State Circuits   36(10) 1587-1591   Oct 2001   [Refereed]
T. Sato, Y. Nishio, T. Sugano, and Y. Nakagome
IEEE Journal of Solid-State Circuits   34(5) 653-660   May 1999   [Refereed]

Misc

 
A Tuning-free Hardware Reservoir Based on MOSFET Crossbar Array for Practical Echo State Network Implementation (accepted)
Y. Kume, S. Bian, and T. Sato
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC)      Jan 2020   [Refereed]
Parameter Extraction Procedure for Surface-potential-based SiC MOSFET Model (accepted)
M. Shintani, H. Tsukamoto, and T. Sato
IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA)      Oct 2019   [Refereed]
A Tuning-free Reservoir of MOSFET Crossbar Array for Inexpensive Hardware Realization of Echo State Network (accepted)
Y. Kume, M. Hiromoto, and T. Sato
The 22nd workshop on synthesis and system integration of mixed information technologies (SASIMI)   (Poster XX-YY)    Oct 2019   [Refereed]
Improved Multiplier Architecture on ASIC for RLWE-based Key Exchange (accepted)
T. Ono, S. Bian, and T. Sato
The 22nd workshop on synthesis and system integration of mixed information technologies (SASIMI)   (Poster XX-YY)    Oct 2019   [Refereed]
Estimation of NBTI-induced Timing Degradation Considering Duty Ratio (accepted)
K. Oshima, S. Bian, and T. Sato
The 22nd workshop on synthesis and system integration of mixed information technologies (SASIMI)   (Poster XX-YY)    Oct 2019   [Refereed]
Heart Rate Estimation During Exercise from Photoplethysmographic Signals Using Convolutional Neural Network (accepted)
M. Nakamura and T. Sato
Biomedical Circuits and Systems Conference (BIOCAS)   vol(no)    Oct 2019   [Refereed]
Experimental Study of Bias Stress Degradation of Organic Thin Film Transistors (accepted)
K. Oshima, M. Saito, M. Shintani, K. Kuribara, Y. Ogasahara, and T. Sato
International Conference on Solid State Devices and Materials (SSDM)   (J-X-YY)    Sep 2019   [Refereed]
A Three-level Active Gate Drive Circuit for Power MOSFETs Utilizing a Generic Gate Driver IC (accepted)
M. Shintani, K. Oishi, and T. Sato
International Conference on Silicon Carbide and Related Materials (ICSCRM)      Sep 2019   [Refereed]
Z. Qin, M. Shintani, K. Kuribara, Y. Ogasahara, and T. Sato
IEEE International Conference on Flexible and Printable Sensors and Systems (FLEPS)   (P-47) XXX-YYY   Jul 2019   [Refereed]
S. Bian, M. Hiromoto, and T. Sato
ACM/IEEE Design Automation Conference (DAC)   52.4:1-52.4:6   Jun 2019   [Refereed]
H. Tsukamoto, M. Shintani, and T. Sato
IEEE International Conference on Microelectronic Test Structures (ICMTS)   107-112   Mar 2019   [Refereed]
M. Saito, M. Shintani, K. Kuribara, Y. Ogasahara, and T. Sato
IEEE International Conference on Microelectronic Test Structures (ICMTS)   194-199   Mar 2019   [Refereed]
S. Bian, M. Hiromoto, and T. Sato
Design, Automation and Test in Europe (DATE)   1718-1723   Mar 2019   [Refereed]
Towards Practical Homomorphic Email Filtering: A Hardware-accelerated Secure Naive Bayesian Filter
S. Bian, M. Hiromoto, and T. Sato
IEICE Technical Report   VLD2018-115 133-138   Feb 2019
S. Bian, M. Hiromoto, and T. Sato
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC)   621-626   Jan 2019   [Refereed]
T. Sato
IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)   1-6   Nov 2018   [Refereed][Invited]
M. Saito, M. Shintani, K. Kuribara, Y. Ogasahara, and T. Sato
IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)   1-6   Nov 2018   [Refereed]
Z. Qin, M. Shintani, K. Kuribara, Y. Ogasahara, and T. Sato
IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)   1-6   Nov 2018   [Refereed]
H. Gyoten, M. Hiromoto, and T. Sato
IEEE/ACM International Conference on Computer-Aided Design (ICCAD)   1-6   Nov 2018   [Refereed]
Initial Parameter Extraction Procedure for Surface-potential-based SiC MOSFET Model
M. Shintani and T. Sato
Workshop on variability modeling and characterization (VMC)   poster-3   Nov 2018   [Refereed]
On the Reset Operation of Organic Cross-coupled Inverter
M. Saito, M. Shintani, K. Kuribara, Y. Ogasahara, M. Hiromoto, and T. Sato
International Conference on Solid State Devices and Materials (SSDM)   (J-3-03) 565-566   Sep 2018   [Refereed]
Y. Fujita, M. Hiromoto, and T. Sato
International Engineering in Medicine and Biology Conference (EMBC)   1-6   Jul 2018   [Refereed]
T. Ujiie, M. Hiromoto, and T. Sato
IEEE Embedded Vision Workshop   729-737   Jun 2018   [Refereed]
S. Bian, M. Hiromoto, and T. Sato
ACM/IEEE Design Automation Conference (DAC)   10.3:1-10.3:6   Jun 2018   [Refereed]
S. Matsumoto, H. Gyoten, M. Hiromoto, and T. Sato
IEEE International Memory Workshop (IMW)   70-73   May 2018   [Refereed]
M. Shintani, B. N. Dauphin, K. Oishi, M. Hiromoto, and T. Sato
International power electronics conference (IPEC)   3644-3649   May 2018   [Refereed]
Coin Flipping PUF: A New PUF With Improved Resistance Against Machine Learning Attacks (accepted)
Y. Tanaka, S. Bian, M. Hiromoto, and T. Sato
IEEE International Symposium on Circuits and Systems (ISCAS)      May 2018   [Refereed]
T. Sato, K. Oishi, M. Hiromoto, and M. Shintani
China Semiconductor Technology International Conference (CSTIC)   (9-23) 1-4   Mar 2018   [Refereed][Invited]
Z. Shin, S. Morita, S. Bian, M. Shintani, M. Hiromoto, and T. Sato
International Symposium on Quality Electronic Design (ISQED)   251-256   Mar 2018   [Refereed]
H. Awano and T. Sato
Design, Automation and Test in Europe (DATE)   1459-1464   Mar 2018   [Refereed]
M. Shintani, M. Hiromoto, and T. Sato
IEEE International Conference on Microelectronic Test Structures (ICMTS)   35-42   Mar 2018   [Refereed]
A PUF Based on the Instantaneous Response of Ring Oscillator Determined by the Convergence Time of Bistable Ring
Y. Tanaka, S. Bian, M. Hiromoto, and T. Sato
The 21st workshop on synthesis and system integration of mixed information technologies (SASIMI)   (Poster R1-6) 30-34   Mar 2018   [Refereed]
A Feasibility Study of Annealing Processor for Fully-connected Ising Model Based on Memristor/CMOS Hybrid Architecture
S. Matsumoto, H. Gyoten, M. Hiromoto, and T. Sato
The 21st workshop on synthesis and system integration of mixed information technologies (SASIMI)   (Poster R1-10) 45-50   Mar 2018   [Refereed]
Comparative Study of Delay Degradation Caused by NBTI Considering Stress Frequency Dependence
Z. Shin, S. Morita, S. Bian, M. Shintani, M. Hiromoto, and T. Sato
The 21st workshop on synthesis and system integration of mixed information technologies (SASIMI)   (Poster R3-2) 194-199   Mar 2018   [Refereed]
Fast and Robust Heart Rate Estimation Using Inexpensive Cameras Through Dynamic Region Selection (accepted)
Y. Fujita, M. Hiromoto, and T. Sato
IEEE Conference on Biomedical and Health Informatics (BHI)      Mar 2018   [Refereed]
S. Morita, S. Bian, M. Shintani, M. Hiromoto, and T. Sato
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC)   631-636   Jan 2018   [Refereed]
Parameter Extraction for MOSFEET Current Model Using Backward Propagation of Errors
M. Shintani, M. Hiromoto, and T. Sato
Workshop on variability modeling and characterization (VMC)   poster-6   Nov 2017   [Refereed]
A Design-analysis Flow Considering Mechanical Stability of Metal Masks for Organic CMOS Circuits
M. Shintani, K. Kuribara, Y. Ogasahara, M. Hiromoto, and T. Sato
International Conference on Solid State Devices and Materials (SSDM)   (B-3-5) 91-92   Sep 2017   [Refereed]
Secured Content Addressable Memory Based on Homomorphic Encryption
S. Bian, M. Hiromoto, and T. Sato
DA Symposium   133-138   Aug 2017   [Refereed]
S. Bian, M. Shintani, M. Hiromoto, and T. Sato
ACM/IEEE Design Automation Conference (DAC)   66:1-66:6   Jun 2017   [Refereed]
S. Morita, S. Bian, M. Shintani, M. Hiromoto, and T. Sato
International Symposium on Quality Electronic Design (ISQED)   426-431   Mar 2017   [Refereed]
K. Oishi, M. Shintani, M. Hiromoto, and T. Sato
IEEE International Conference on Microelectronic Test Structures (ICMTS)   87-92   Mar 2017   [Refereed]
S. Bian, M. Hiromoto, and T. Sato
Design, Automation and Test in Europe (DATE)   984-989   Mar 2017   [Refereed]
M. Shintani, K. Oishi, R. Zhou, M. Hiromoto, and T. Sato
IEEE Applied Power Electronics Conference and Exposition (APEC)   1001-1006   Mar 2017   [Refereed]
H. Awano, M. Hiromoto, and T. Sato
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC)   93-98   Jan 2017   [Refereed]
Y. Chen, M. Shintani, T. Sato, Y. Shi, and S. Chang
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC)   543-548   Jan 2017   [Refereed]
Hardware Accelerator of Convolutional Neural Network for Image Recognition and Its Performance Evaluation Platform
T. Ujiie, M. Hiromoto, and T. Sato
The 20th workshop on synthesis and system integration of mixed information technologies (SASIMI)   (Poster R1-4) 16-17   Nov 2016   [Refereed]
Path Grouping Approach for Efficient Candidate-selection of Replacing NBTI Mitigation Logic
S. Morita, S. Bian, M. Shintani, M. Hiromoto, and T. Sato
The 20th workshop on synthesis and system integration of mixed information technologies (SASIMI)   (poster R3-12) 225-230   Nov 2016   [Refereed]
Thermal Circuit Identification of Power MOSFETs Through In-situ Channel Temperature Estimation
K. Oishi, M. Shintani, M. Hiromoto, and T. Sato
The 20th workshop on synthesis and system integration of mixed information technologies (SASIMI)   (Poster R3-15) 242-247   Nov 2016   [Refereed]
Unique Device Identification Framework for Power MOSFETs Using Inherent Device Variation
M. Shintani, K. Oishi, R. Zhou, M. Hiromoto, and T. Sato
Workshop on variability modeling and characterization (VMC)   poster-7   Nov 2016   [Refereed]
Representative Path Approach for Time-efficient NBTI Mitigation Logic Replacement
S. Morita, S. Bian, M. Shintani, M. Hiromoto, and T. Sato
Workshop on variability modeling and characterization (VMC)   poster-8   Nov 2016   [Refereed]
T. Okuda, Y. Nakamura, M. Shintani, T. Sato, and T. Hikihara
IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA)   101-104   Nov 2016   [Refereed]
M. Shintani, K. Oishi, R. Zhou, M. Hiromoto, and T. Sato
IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA)   286-289   Nov 2016   [Refereed]
K. Oishi, M. Shintani, M. Hiromoto, and T. Sato
IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA)   308-313   Nov 2016   [Refereed]
S. Bian, M. Shintani, Z. Wang, M. Hiromoto, A. Chattopadhyay, and T. Sato
IEEE Asian Test Symposium (ATS)   234-239   Nov 2016   [Refereed]
A Charge Based SiC Power MOSFET Model Considering On-state Resistance
R. Zhou, M. Shintani, M. Hiromoto, and T. Sato
International Symposium on Nonlinear Theory and Its Applications (NOLTA)   177-180   Nov 2016   [Refereed]
A Design Example of Class-E Based Gate Driver for High Frequency Operation of SiC Power MOSFET
M. Shintani, S. Yuchong, H. Sekiya, and T. Sato
International Symposium on Nonlinear Theory and Its Applications (NOLTA)   181-181   Nov 2016   [Refereed]
T. Ujiie, M. Hiromoto, and T. Sato
IEEE Embedded Vision Workshop   52-58   Sep 2016   [Refereed]
Y. Nakamura, M. Shintani, K. Oishi, T. Sato, and T. Hikihara
International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)   121-124   Sep 2016   [Refereed]
Aging-aware Timing Analysis Based on Machine Learning
S. Bian, M. Shintani, M. Hiromoto, and T. Sato
DA Symposium   44-49   Sep 2016   [Refereed]
A Surface-potential-based Reverse-transfer Capacitance Model for Vertical SiC DMOSFET
M. Shintani, Y. Nakamura, M. Hiromoto, and T. Sato
International Conference on Solid State Devices and Materials (SSDM)   993-994   Sep 2016   [Refereed]
H. Awano and T. Sato
ACM/IEEE Design Automation Conference (DAC)   115:1-115:6   Jun 2016   [Refereed]
S. Bian, M. Shintani, S. Morita, H. Awano, M. Hiromoto, and T. Sato
ACM Great Lakes Symposium on VLSI (GLSVLSI)   203-208   May 2016   [Refereed]
M. Yoshinaga, H. Awano, M. Hiromoto, and T. Sato
IEEE International Symposium on Circuits and Systems (ISCAS)   2619-2622   May 2016   [Refereed]
Mitigation of NBTI-induced Timing Degradation in Processor
S. Bian, M. Shintani, Z. Wang, M. Hiromoto, A. Chattopadhyay, and T. Sato
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)   21-27   Mar 2016   [Refereed]
Efficient Transistor-level Timing Yield Estimation via Line Sampling
H. Awano and T. Sato
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)   50-55   Mar 2016   [Refereed]
S. Bian, M. Shintani, S. Morita, M. Hiromoto, and T. Sato
International Symposium on Quality Electronic Design (ISQED)   307-312   Mar 2016   [Refereed]
Y. Nakamura, M. Shintani, T. Sato, and T. Hikihara
IEEE International Conference on Microelectronic Test Structures (ICMTS)   90-94   Mar 2016   [Refereed]
Fast Monte Carlo for Timing Yield Estimation via Line Sampling
H. Awano and T. Sato
Workshop on variability modeling and characterization (VMC)   poster-2   Nov 2015
Fast Estimation on NBTI-induced Delay Degradation Based on Signal Probability
S. Bian, M. Shintani, M. Hiromoto, and T. Sato
DA Symposium   181-186   Aug 2015   [Refereed]
H. Awano, M. Hiromoto, and T. Sato
Design, Automation and Test in Europe (DATE)   549-554   Mar 2015   [Refereed]
Accelerating Random-walk-based Power Grid Analysis Through Error Smoothing
T. Okazaki, M. Hiromoto, and T. Sato
The 19th workshop on synthesis and system integration of mixed information technologies (SASIMI)   362-367   Mar 2015   [Refereed]
M. Shintani and T. Sato
IEEE/ACM International Conference on Computer-Aided Design (ICCAD)   498-502   Nov 2014   [Refereed]
A Case Study of Chinese Calligraphic Style Classification Using Deep Neural Network
M. Hiromoto and T. Sato
International Workshop on Smart Info-Media Systems in Asia (SISA)   SS3-05   Oct 2014   [Refereed]
C. Nitschke, Y. Minami, M. Hiromoto, H. Ohshima, and T. Sato
14th International Conference on Control, Automation and Systems (ICCAS 2014)   678-685   Oct 2014   [Refereed]
T. Sato, H. Awano, and M. Hiromoto
IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)   255-258   Oct 2014   [Refereed][Invited]
H. Awano, M. Hiromoto, and T. Sato
Solid-State Device Research Conference (ESSDERC)   218-221   Sep 2014   [Refereed]
An Experimental Study on Interdigital Capacitance Sensor for Detecting Heart Rate
X. Cao, M. Hiromoto, and T. Sato
Workshop on Circuits and Systems   138-143   Aug 2014   [Refereed]
A Low Cost Capacitor Approach for Suppressing Resonance in Power Distribution Networks
K. Yamanaga, H. Yamamoto, and T. Sato
International Symposium on Electromagnetic Compatibility, Tokyo (EMC Tokyo)   346-349   May 2014   [Refereed]
T. Sato, J. Kawashima, H. Tsutsui, and H. Ochi
International Symposium on Quality Electronic Design (ISQED)   428-433   Mar 2014   [Refereed]
Time Dependent Degradation (Invited)
T. Sato and M. Hashimoto
The Journal of Reliability Engineering Association of Japan   35(8) 457-458   Dec 2013   [Refereed][Invited]
Statistical Observation of NBTI and PBTI Degradations
H. Awano, M. Hiromoto, and T. Sato
Workshop on variability modeling and characterization (VMC)   poster-03   Nov 2013
A Device Array for Flexible BTI Characterization (Invited Talk)
T. Sato
Workshop on variability modeling and characterization (VMC)   talk-06   Nov 2013
Place-and-route Algorithms for a Reliability-oriented Coarse-grained Reconfigurable Architecture Using Time Redundancy
T. Imagawa, M. Hiromoto, H. Tsutsui, H. Ochi, and T. Sato
The 18th workshop on synthesis and system integration of mixed information technologies (SASIMI)   76-81   Oct 2013   [Refereed]
T. Sato
The IEEE 10th International Conference on ASIC (ASICON)   103-106   Sep 2013   [Refereed][Invited]
Histogram Propagation Based Statistical Timing Analysis Using Dependent Node Selection
S. Zhang, H. Tsutsui, H. Ochi, and T. Sato
The 28th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)   321-324   Jun 2013   [Refereed]
Architecture for Sealed Wafer-scale Mask ROM for Long-term Digital Data Preservation
S. Matsuda, T. Imagawa, H. Tsutsui, T. Sato, Y. Nakamura, and H. Ochi
The 28th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)   274-277   Jun 2013   [Refereed]
T. Morishita, H. Tsutsui, H. Ochi, and T. Sato
ACM Great Lakes Symposium on VLSI (GLSVLSI)   95-100   May 2013   [Refereed]
J. B. Velamala, K. B. Sutaria, H. Shimizu, H. Awano, T. Sato, G. Wirth, and Y. Cao
IEEE International Reliability Physics Symposium (IRPS)   CM.3.1-CM.3.5   Apr 2013   [Refereed]
H. Awano, H. Tsutsui, H. Ochi, and T. Sato
International Symposium on Quality Electronic Design (ISQED)   613-618   Mar 2013   [Refereed]
T. Imagawa, H. Tsutsui, H. Ochi, and T. Sato
International Symposium on Quality Electronic Design (ISQED)   554-561   Mar 2013   [Refereed]
[Memorial Lecture] an Adaptive Current-threshold Determination for IDDQ Testing Based on Bayesian Process Parameter Estimation
M. Shintani and T. Sato
IEICE Technical Report   VLD2012-152 91-91   Mar 2013
Evaluation of Dependent Node Selection of Histogram Propagation Based Statistical Timing Analysis
S. Zhang, H. Tsutsui, H. Ochi, and T. Sato
IEICE general conference   (62) A-3   Mar 2013
Z. E. Rakossy, M. Hiromoto, H. Tsutsui, T. Sato, Y. Nakamura, and H. Ochi
Design, Automation and Test in Europe (DATE)   535-540   Mar 2013   [Refereed]
T. Imagawa, H. Tsutsui, H. Ochi, and T. Sato
Design, Automation and Test in Europe (DATE)   701-706   Mar 2013   [Refereed]
T. Miyakawa, H. Tsutsui, H. Ochi, and T. Sato
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC)   169-174   Jan 2013   [Refereed]
M. Shintani and T. Sato
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC)   614-619   Jan 2013   [Refereed]
Adaptive Current-threshold Determination for Accurate IDDQ Testing
M. Shintani and T. Sato
Workshop on variability modeling and characterization (VMC)   poster-10   Nov 2012
Accurate I/O Buffer Impedance Self-adjustment Using Vth and Temperature Sensors
Z. Li, H. Tsutsui, H. Ochi, and T. Sato
Design gaia, SLDM society conference   VLD2012-79 117-122   Nov 2012
K. Yamanaga and T. Sato
The 21st conference on electrical performance of electronic packaging and systems (EPEPS)   256-259   Oct 2012   [Refereed]

Books etc

 
VLSI Design and Test for Systems Dependability
Takashi Sato (Part:Contributor, Chapter 6, Time-Dependent Degradation in Device Characteristics and Countermeasures by Design)
Springer   Apr 2019   ISBN:978-4-431-56592-5
Circuit Design for Reliability
Reis, Cao, Wirth (Part:Contributor, Chapter 5)
Springer   Nov 2014   ISBN:978-1-4614-4077-2
Bias Temperature Instability for Devices and Circuits
Grasser, Tibor (Ed.) (Part:Contributor, Chapter 19 and 20, pp.719-782,)
Springer   Dec 2013   

Conference Activities & Talks

 
A Plotter-based Automatic Measurements and Statistical Characterization of Multiple Discrete Power Devices (accepted)
M. Shintani, B. N. Dauphin, K. Oishi, M. Hiromoto, and T. Sato
International power electronics conference (IPEC)   May 2018   
Ising-PUF: A Machine Learning Attack Resistant PUF Featuring Lattice Like Arrangement of Arbiter-PUFs (accepted)
H. Awano and T. Sato
Design, Automation and Test in Europe (DATE)   Mar 2018   
A Study on NBTI-induced Delay Degradation Considering Stress Frequency Dependence (accepted)
Z. Shin, S. Morita, S. Bian, M. Shintani, M. Hiromoto, and T. Sato
International Symposium on Quality Electronic Design (ISQED)   Mar 2018   
Comparative Study of Delay Degradation Caused by NBTI Considering Stress Frequency Dependence (accepted)
Z. Shin, S. Morita, S. Bian, M. Shintani, M. Hiromoto, and T. Sato
The 21st workshop on synthesis and system integration of mixed information technologies (SASIMI)   Mar 2018   
A PUF Based on the Instantaneous Response of Ring Oscillator Determined by the Convergence Time of Bistable Ring (accepted)
Y. Tanaka, S. Bian, M. Hiromoto, and T. Sato
The 21st workshop on synthesis and system integration of mixed information technologies (SASIMI)   Mar 2018   
A Feasibility Study of Annealing Processor for Fully-Connected Ising Model Based on Memristor/CMOS Hybrid Architecture (accepted)
S. Matsumoto, H. Gyoten, M. Hiromoto, and T. Sato
The 21st workshop on synthesis and system integration of mixed information technologies (SASIMI)   Mar 2018   
Electrical and Thermal Characterization of SiC Power MOSFET (Invited) (accepted) [Invited]
T. Sato, K. Oishi, M. Hiromoto, and M. Shintani
China Semiconductor Technology International Conference (CSTIC)   Mar 2018   
Efficient Exploration of Worst Case Workload and Timing Degradation Under NBTI (accepted)
S. Morita, S. Bian, M. Shintani, M. Hiromoto, and T. Sato
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC)   Jan 2018   
Parameter Extraction for MOSFEET Current Model Using Backward Propagation of Errors
M. Shintani, M. Hiromoto, and T. Sato
Workshop on variability modeling and characterization (VMC)   Nov 2017   
A Design-analysis Flow Considering Mechanical Stability of Metal Masks for Organic CMOS Circuits
M. Shintani, K. Kuribara, Y. Ogasahara, M. Hiromoto, and T. Sato
IEEE International Conference on Solid State Devices and Materials (SSDM)   Sep 2017   
Secured Content Addressable Memory Based on Homomorphic Encryption
S. Bian, M. Hiromoto, and T. Sato
DA Symposium   Aug 2017   
LSTA: Learning-based Static Timing Analysis for High-dimensional Correlated On-chip Variations
S. Bian, M. Shintani, M. Hiromoto, and T. Sato
ACM/IEEE Design Automation Conference (DAC)   Jun 2017   
Comparative Study of Path Selection and Objective Function in Replacing NBTI Mitigation Logic
S. Morita, S. Bian, M. Shintani, M. Hiromoto, and T. Sato
International Symposium on Quality Electronic Design (ISQED)   Mar 2017   
Input Capacitance Determination of Power MOSFETs from Switching Trajectories
K. Oishi, M. Shintani, M. Hiromoto, and T. Sato
IEEE International Conference on Microelectronic Test Structures (ICMTS)   Mar 2017   
SCAM: Secured Content Addressable Memory Based on Homomorphic Encryption
S. Bian, M. Hiromoto, and T. Sato
Design, Automation and Test in Europe (DATE)   Mar 2017   
Device Identification from Mixture of Measurable Characteristics
M. Shintani, K. Oishi, R. Zhou, M. Hiromoto, and T. Sato
IEEE Applied Power Electronics Conference and Exposition (APEC)   Mar 2017   
Efficient Circuit Failure Probability Calculation Along Product Lifetime Considering Device Aging
H. Awano, M. Hiromoto, and T. Sato
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC)   Jan 2017   
Pattern Based Runtime Voltage Emergency Prediction: An Instruction-aware Block Sparse Compressed Sensing Approach
Y. Chen, M. Shintani, T. Sato, Y. Shi, and S. Chang
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC)   Jan 2017   
Hardware Accelerator of Convolutional Neural Network for Image Recognition and Its Performance Evaluation Platform
T. Ujiie, M. Hiromoto, and T. Sato
The 20th workshop on synthesis and system integration of mixed information technologies (SASIMI)   Nov 2016   
Path Grouping Approach for Efficient Candidate-selection of Replacing NBTI Mitigation Logic
S. Morita, S. Bian, M. Shintani, M. Hiromoto, and T. Sato
The 20th workshop on synthesis and system integration of mixed information technologies (SASIMI)   Nov 2016   
Thermal Circuit Identification of Power MOSFETs Through In-situ Channel Temperature Estimation
K. Oishi, M. Shintani, M. Hiromoto, and T. Sato
The 20th workshop on synthesis and system integration of mixed information technologies (SASIMI)   Nov 2016   
Unique Device Identification Framework for Power MOSFETs Using Inherent Device Variation
M. Shintani, K. Oishi, R. Zhou, M. Hiromoto, and T. Sato
Workshop on variability modeling and characterization (VMC)   Nov 2016   
Representative Path Approach for Time-efficient NBTI Mitigation Logic Replacement
S. Morita, S. Bian, M. Shintani, M. Hiromoto, and T. Sato
Workshop on variability modeling and characterization (VMC)   Nov 2016   
Analysis of Transient Behavior of SiC Power MOSFETs Based on Surface Potential Model and Its Application to Boost Converter
T. Okuda, Y. Nakamura, M. Shintani, T. Sato, and T. Hikihara
IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA)   Nov 2016   
A Circuit Simulation Model for V-groove SiC Power MOSFET
M. Shintani, K. Oishi, R. Zhou, M. Hiromoto, and T. Sato
IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA)   Nov 2016   
Identifications of Thermal Equivalent Circuit for Power MOSFETs Through In-situ Channel Temperature Estimation
K. Oishi, M. Shintani, M. Hiromoto, and T. Sato
IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA)   Nov 2016   
Runtime NBTI Mitigtion for Processor Lifespan Extension via Selective Node Control
S. Bian, M. Shintani, Z. Wang, M. Hiromoto, A. Chattopadhyay, and T. Sato
IEEE Asian Test Symposium (ATS)   Nov 2016   
A Charge Based SiC Power MOSFET Model Considering On-state Resistance
R. Zhuo, M. Shintani, M. Hiromoto, and T. Sato
International Symposium on Nonlinear Theory and Its Applications (NOLTA)   Nov 2016   
A Design Example of Class-E Based Gate Driver for High Frequency Operation of SiC Power MOSFET
M. Shintani, S. Yuchong, H. Sekiya, and T. Sato
International Symposium on Nonlinear Theory and Its Applications (NOLTA)   Nov 2016   
Approximated Prediction Strategy for Reducing Power Consumption of Convolutional Neural Network Processor
T. Ujiie, M. Hiromoto, and T. Sato
Embedded Vision Workshop   Sep 2016   
A Simulation Model for SiC Power MOSFET Based on Surface Potential
Y. Nakamura, M. Shintani, K. Oishi, T. Sato, and T. Hikihara
International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)   Sep 2016   
Aging-aware Timing Analysis Based on Machine Learning
S. Bian, M. Shintani, M. Hiromoto, and T. Sato
DA Symposium   Sep 2016   
A Surface-potential-based Reverse-transfer Capacitance Model for Vertical SiC DMOSFET
M. Shintani, Y. Nakamura, M. Hiromoto, and T. Sato
IEEE International Conference on Solid State Devices and Materials (SSDM)   Sep 2016   
Efficient Transistor-level Timing Yield Estimation via Line Sampling
H. Awano and T. Sato
ACM/IEEE Design Automation Conference (DAC)   Jun 2016   
Workload-aware Worst Path Analysis of Processor-scale NBTI Degradation
S. Bian, M. Shintani, S. Morita, H. Awano, M. Hiromoto, and T. Sato
ACM Great Lakes Symposium on VLSI (GLSVLSI)   May 2016   
Physically Unclonable Function Using RTN-induced Delay Fluctuation in Ring Oscillators
M. Yoshinaga, H. Awano, M. Hiromoto, and T. Sato
IEEE International Symposium on Circuits and Systems (ISCAS)   May 2016   
Mitigation of NBTI-induced Timing Degradation in Processor
S. Bian, M. Shintani, Z. Wang, M. Hiromoto, A. Chattopadhyay, and T. Sato
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)   Mar 2016   
Efficient Transistor-level Timing Yield Estimation via Line Sampling
H. Awano and T. Sato
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)   Mar 2016   
Nonlinear Delay-table Approach for Full-chip NBTI Degradation Prediction
S. Bian, M. Shintani, S. Morita, M. Hiromoto, and T. Sato
International Symposium on Quality Electronic Design (ISQED)   Mar 2016   
A High Power Curve Tracer for Characterizing Full Operational Range of SiC Power Transistors
Y. Nakamura, M. Shintani, T. Sato, and T. Hikihara
IEEE International Conference on Microelectronic Test Structures (ICMTS)   Mar 2016   
Fast Monte Carlo for Timing Yield Estimation via Line Sampling
H. Awano and T. Sato
Workshop on variability modeling and characterization (VMC)   Nov 2015   
Fast Estimation on NBTI-induced Delay Degradation Based on Signal Probability
S. Bian, M. Shintani, M. Hiromoto, and T. Sato
DA Symposium   Aug 2015   
ECRIPSE: An Efficient Method for Calculating RTN-induced Failure Probability of an SRAM Cell
H. Awano, M. Hiromoto, and T. Sato
Design, Automation and Test in Europe (DATE)   Mar 2015   
Accelerating Random-walk-based Power Grid Analysis Through Error Smoothing
T. Okazaki, M. Hiromoto, and T. Sato
The 19th workshop on synthesis and system integration of mixed information technologies (SASIMI)   Mar 2015   
Sensorless Estimation of Global Device-parameters Through Fmax Testing
M. Shintani and T. Sato
IEEE/ACM International Conference on Computer-Aided Design (ICCAD)   Nov 2014   
A Case Study of Chinese Calligraphic Style Classification Using Deep Neural Network
M. Hiromoto and T. Sato
International Workshop on Smart Info-Media Systems in Asia (SISA)   Oct 2014   
A Quadrocopter Automatic Control Contest as an Example of Interdisciplinary Design Education
C. Nitschke, Y. Minami, M. Hiromoto, H. Ohshima, and T. Sato
14th International Conference on Control, Automation and Systems (ICCAS 2014)   Oct 2014   
A Scalable Device Array for Statistical Device-aging Characterization (Invited) [Invited]
T. Sato, H. Awano, and M. Hiromoto
IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)   Oct 2014   
Variability in Device Degradations: Statistical Observation of NBTI for 3996 Transistors
H. Awano, M. Hiromoto, and T. Sato
Solid-State Device Research Conference (ESSDERC)   Sep 2014   
An Experimental Study on Interdigital Capacitance Sensor for Detecting Heart Rate
X. Cao, M. Hiromoto, and T. Sato
Workshop on Circuits and Systems   Aug 2014   
A Low Cost Capacitor Approach for Suppressing Resonance in Power Distribution Networks
K. Yamanaga, H. Yamamoto, and T. Sato
International Symposium on Electromagnetic Compatibility, Tokyo (EMC Tokyo)   May 2014   
Experimental Validation of Minimum Operating Voltage Estimation for Low Supply Voltage Circuits
T. Sato, J. Kawashima, H. Tsutsui, and H. Ochi
International Symposium on Quality Electronic Design (ISQED)   Mar 2014   
Time Dependent Degradation (Invited) [Invited]
T. Sato and M. Hashimoto
The Journal of Reliability Engineering Association of Japan   Dec 2013   
Statistical Observation of NBTI and PBTI Degradations
H. Awano, M. Hiromoto, and T. Sato
Workshop on variability modeling and characterization (VMC)   Nov 2013   
A Device Array for Flexible BTI Characterization (Invited Talk)
T. Sato
Workshop on variability modeling and characterization (VMC)   Nov 2013   
Place-and-route Algorithms for a Reliability-oriented Coarse-grained Reconfigurable Architecture Using Time Redundancy
T. Imagawa, M. Hiromoto, H. Tsutsui, H. Ochi, and T. Sato
The 18th workshop on synthesis and system integration of mixed information technologies (SASIMI)   Oct 2013   
Statistical Simulation Methods for Analyzing Performance of Low Supply Voltage Circuits (Invited) [Invited]
T. Sato
The IEEE 10th International Conference on ASIC (ASICON)   Sep 2013   
Histogram Propagation Based Statistical Timing Analysis Using Dependent Node Selection
S. Zhang, H. Tsutsui, H. Ochi, and T. Sato
The 28th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)   Jun 2013   
Architecture for Sealed Wafer-scale Mask ROM for Long-term Digital Data Preservation
S. Matsuda, T. Imagawa, H. Tsutsui, T. Sato, Y. Nakamura, and H. Ochi
The 28th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)   Jun 2013   
Fast and Memory-efficient GPU Implementations of Krylov Subspace Methods for Efficient Power Grid Analysis
T. Morishita, H. Tsutsui, H. Ochi, and T. Sato
ACM Great Lakes Symposium on VLSI (GLSVLSI)   May 2013   
Logarithmic Modeling of BTI Under Dynamic Circuit Operations: Static, Dynamic and Long-term Prediction
J. B. Velamala, K. B. Sutaria, H. Shimizu, H. Awano, T. Sato, G. Wirth, and Y. Cao
IEEE International Reliability Physics Symposium (IRPS)   Apr 2013   
Multi-trap RTN Parameter Extraction Based on Bayesian Inference
H. Awano, H. Tsutsui, H. Ochi, and T. Sato
International Symposium on Quality Electronic Design (ISQED)   Mar 2013   
High-speed DFG-level SEU Vulnerability Analysis for Applying Selective TMR to Resource-constrained CGRA
T. Imagawa, H. Tsutsui, H. Ochi, and T. Sato
International Symposium on Quality Electronic Design (ISQED)   Mar 2013   
[Memorial Lecture] an Adaptive Current-threshold Determination for IDDQ Testing Based on Bayesian Process Parameter Estimation
M. Shintani and T. Sato
IEICE Technical Report   Mar 2013   
Evaluation of Dependent Node Selection of Histogram Propagation Based Statistical Timing Analysis
S. Zhang, H. Tsutsui, H. Ochi, and T. Sato
IEICE general conference   Mar 2013   
Hot-swapping Architecture With Back-biased Testing for Mitigation of Permanent Faults in Functional Unit Array
Z. E. Rakossy, M. Hiromoto, H. Tsutsui, T. Sato, Y. Nakamura, and H. Ochi
Design, Automation and Test in Europe (DATE)   Mar 2013   
A Cost-effective Selective TMR for Heterogeneous Coarse-grained Reconfigurable Architectures Based on DFG-level Vulnerability Analysis
T. Imagawa, H. Tsutsui, H. Ochi, and T. Sato
Design, Automation and Test in Europe (DATE)   Mar 2013   
Realization of Frequency-domain Circuit Analysis Through Random Walk
T. Miyakawa, H. Tsutsui, H. Ochi, and T. Sato
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC)   Jan 2013   
An Adaptive Current-threshold Determination for IDDQ Testing Based on Bayesian Process Parameter Estimation
M. Shintani and T. Sato
ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC)   Jan 2013   
Adaptive Current-threshold Determination for Accurate IDDQ Testing
M. Shintani and T. Sato
Workshop on variability modeling and characterization (VMC)   Nov 2012   
Accurate I/O Buffer Impedance Self-adjustment Using Vth and Temperature Sensors
Z. Li, H. Tsutsui, H. Ochi, and T. Sato
Design gaia, SLDM society conference   Nov 2012   
The Odd Couple: Antiresonance Control by Two Capacitors of Unequal Series Resistances
K. Yamanaga and T. Sato
The 21st conference on electrical performance of electronic packaging and systems (EPEPS)   Oct 2012   
Statistical Aging Under Dynamic Voltage Scaling: A Logarithmic Model Approach
J. B. Velamala, K. B. Sutaria, H. Shimizu, H. Awano, T. Sato, and Y. Cao
IEEE Custom Integrated Circuits Conference (CICC)   Sep 2012   
Physics Matters: Statistical Aging Prediction Under Trapping/detrapping
J. B. Velamala, K. B. Sutaria, T. Sato, and Y. Cao
ACM/IEEE Design Automation Conference (DAC)   Jun 2012   
Aging Statistics Based on Trapping/detrapping: Silicon Evidence, Modeling and Long-term Prediction
J. B. Velamala, K. B. Sutaria, T. Sato, and Y. Cao
IEEE International Reliability Physics Symposium (IRPS)   Apr 2012   
A Bayesian-based Process Parameter Estimation Using IDDQ Current Signature
M. Shintani and T. Sato
IEEE VLSI Test Symposium (VTS)   Apr 2012   
Hardware Architecture for Accelerating Monte Carlo Based SSTA Using Generalized STA Processing Element
H. Yuasa, H. Tsutsui, H. Ochi, and T. Sato
The 17th workshop on synthesis and system integration of mixed information technologies (SASIMI)   Mar 2012   
GPU Acceleration of Cycle-based Soft-error Simulation for Reconfigurable Array Architectures
T. Imagawa, T. Oue, H. Tsutsui, H. Ochi, and T. Sato
The 17th workshop on synthesis and system integration of mixed information technologies (SASIMI)   Mar 2012   
Statistical Observations of NBTI-induced Threshold Voltage Shifts on Small Channel-area Devices
T. Sato, H. Awano, H. Shimizu, H. Tsutsui, and H. Ochi
International Symposium on Quality Electronic Design (ISQED)   Mar 2012   
Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element
H. Yuasa, H. Tsutsui, H. Ochi, and T. Sato
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)   Jan 2012   
Getting the Most Out of IDDQ Testing
M. Shintani and T. Sato
Workshop on variability modeling and characterization (VMC)   Nov 2011   
Statistical Aging Prediction and Characterization Using Trapping/detrapping Based NBTI Models
J. B. Velamala, T. Sato, and Y. Cao
Workshop on variability modeling and characterization (VMC)   Nov 2011   
A Device Array for Efficient Bias-temperature Instability Measurements
T. Sato, T. Kozaki, T. Uezono, H. Tsutsui, and H. Ochi
Solid-State Device Research Conference (ESSDERC)   Sep 2011   
A Design Strategy for Sub-threshold Circuits Considering Energy-minimization and Yield-maximization
J. Kawashima, H. Tsutsui, H. Ochi, and T. Sato
IEEE International SOC Conference (SOCC)   Sep 2011   
A Sensor-based Self-adjustment Approach for Controlling I/O Buffer Impedance
Z. Li, H. Tsutsui, H. Ochi, and T. Sato
IEICE society conference   Sep 2011   
A Stress-parallelized Device Array for Efficient Bias-temperature Stability Measurement
T. Sato, T. Kozaki, T. Uezono, H. Tsutsui, and H. Ochi
The 5th IEEE International Workshop on Design for Manufacturability & Yield (DFM&Y)   Jun 2011   
Acceleration of Random-walk-based Linear Circuit Analysis Using Importance Sampling
T. Miyakawa, K. Yamanaga, H. Tsutsui, H. Ochi, and T. Sato
ACM Great Lakes Symposium on VLSI (GLSVLSI)   May 2011   
A Fully Pipelined Implementation of Monte Carlo Based SSTA on FPGAs
H. Yuasa, H. Tsutsui, H. Ochi, and T. Sato
International Symposium on Quality Electronic Design (ISQED)   Mar 2011   
Sequential Importance Sampling for Low-probability and High-dimensional SRAM Yield Analysis
K. Katayama, S. Hagiwara, H. Tsutsui, H. Ochi, and T. Sato
IEEE/ACM International Conference on Computer-Aided Design (ICCAD)   Nov 2010   
A Transistor-array for Parallel BTI-effects Measurements
T. Uezono, T. Kozaki, H. Ochi, and T. Sato
Workshop on variability modeling and characterization (VMC)   Nov 2010   
A Tool Chain for Generating SEU-vulnerability Map for Coarse-grained Reconfigurable Architecture
T. Imagawa, M. Hiromoto, H. Ochi, and T. Sato
The 25th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)   Jul 2010   
A Routing Architecture Exploration for Coarse-grained Reconfigurable Architecture With Automated SEU-tolerance Evaluation
T. Imagawa, M. Hiromoto, H. Ochi, and T. Sato
IEEE International SOC Conference (SOCC)   Jul 2010   
Application of Generalized Scattering Matrix for Prediction of Power Supply Noise
K. Yamanaga, K. Masu, and T. Sato
ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)   Jun 2010   
Decomposition of Drain-current Variation Into Gain-factor and Threshold Voltage Variations
T. Sato, T. Uezono, N. Nakayama, and K. Masu
IEEE International Symposium on Circuits and Systems (ISCAS)   May 2010   
Small Delay and Area Overhead Process Parameter Estimation Through Path-delay Inequalities
T. Uezono, T. Takahashi, M. Shintani, K. Hatayama, K. Masu, H. Ochi, and T. Sato
IEEE International Symposium on Circuits and Systems (ISCAS)   May 2010   
Path Clustering for Adaptive Test
T. Uezono, T. Takahashi, M. Shintani, K. Hatayama, K. Masu, H. Ochi, and T. Sato
IEEE VLSI Test Symposium (VTS)   Apr 2010   
Sequential Importance Sampling for Low-probability and High-dimensional SRAM Yield Analysis
K. Katayama, T. Date, H. Ochi, and T. Sato
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)   Mar 2010   
Robust Importance Sampling for Efficient SRAM Yield Analysis
T. Date, S. Hagiwara, K. Masu, and T. Sato
International Symposium on Quality Electronic Design (ISQED)   Mar 2010   
Linear Time Calculation of State-dependent Power Distribution Network Capacitance
S. Hagiwara, K. Yamanaga, R. Takahashi, K. Masu, H. Ochi, and T. Sato
International Symposium on Quality Electronic Design (ISQED)   Mar 2010   
On-die Parameter Extraction from Path-delay Measurements
T. Takahashi, T. Uezono, M. Shintani, K. Masu, and T. Sato
IEEE Asian solid-state circuit conference (ASSCC)   Nov 2009