Since the thickness of the stacked silicon chips in 3D integration has been thinned to less than 100 μm, the local thermal deformation of the chips has increased drastically because of the decrease of the flexural rigidity of the thinned chips. The clear periodic thermal deformation and thus, the thermal residual stress distribution appear in the stacked chips due to the periodic alignment of metallic bumps, and they deteriorate the reliability of products. In this paper, the dominant structural factors of the local deformation of a silicon chip are discussed quantitatively based on the results of a three-dimensional finite element analysis and the measurement of the local deformation and residual stress in a chip using strain sensor chips and interference microscopy. ©2010 IEEE.