小菅 敦丈

The design flow for the Agile-Chip platform 

Design and Verification Conference and Exhibition Japan 2026年9月  

3D Orthogonal Die Stacking Technology for DRAM-on-GPU Integration Using Contactless Die-to-Die Interface 

IEEE Symposium on VLSI Circuits 2026年6月  査読有り最終著者責任著者

First Demonstration of MicroBump-based Massive Orthogonal Stacking Assembly IC (MOSAIC) Cube for SoC-DRAM Direct Stacking 

IEEE 76th Electronic Components and Technology Conference (ECTC) 2026年5月  査読有り最終著者責任著者

A 3-Day ASIC Design Hands-on with the Minimal Fab 

IEEE International Symposium on Circuits and Systems (ISCAS) 2026年5月  査読有り

Driving PMUT with Processor-Controlled VCO Realized by Rapid Mixed-Signal Prototyping on Agile-X Platform 

Design, Test, Integration, and Packaging (DTIP) 2026年5月  査読有り

Flipchip-to-Measure” 160-pins Batch Wiring for Quick and Reliable Agile-X VLSI Packaging 

Design, Test, Integration, and Packaging (DTIP) 2026年5月  査読有り

Agile prototyping of AI hardware LSIs using multi-layer aluminum interconnects in a minimal fab environment 

Japanese Journal of Applied Physics 65(8) 088004-088004 2026年4月28日  査読有り

Analysis and design of an oblong coil pair for an edge-coupled inductive link 

Japanese Journal of Applied Physics 65(7) 07SP16-07SP16 2026年4月9日  査読有り最終著者責任著者

Quick design and fabrication of chips with Agile-Chip Platform 

IEEE CoolChips 2026年4月  

A Wired-Logic and Near-Memory Hybrid Processor for General-Purpose Audio Inference Using a Self-Supervised Encoder 

IEEE Open Journal of the Solid-State Circuits Society 2026年  

A 28-nm 0.8M-Weights/mm2 9.1-TOPS/mm2 All-Analog SRAM-Based Compute-in-Memory Macro Using Fine-Grained Structured Pruning With Adaptive-Ranging ADC 

IEEE Transactions on Circuits and Systems I: Regular Papers 2026年  

Analysis and Design of Oblong Coils and Standard-Cell-Based Receiver for Area-Efficient Edge-Coupled Inductive Coupling Transceiver. 

ASP-DAC 223-226 2026年  

A Connectivity-Aware Via-Programmable DNN Processor Using a Single Photomask 

IEEE Open Journal of Circuits and Systems 2026年  

Digital Neuromorphic Processor with Orthogonal 3D Chip Stacking 

JSAP International Microprocesses and Nanotechnology Conference 2025年11月  招待有り筆頭著者最終著者責任著者

Quickly developed chips with the Agile-Chip Platform 

IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2025年10月  査読有り

Hardware and Software Co-Designed Neuron Array Processor for AI-IoT Applications 

IEEE International Parallel and Distributed Processing Symposium (IPDPS), Workshop on Coarse-Grained Reconfigurable Architectures for High-Performance Computing and AI (CGRA4HPCA) 2025年6月  招待有り筆頭著者最終著者責任著者

Massive Orthogonal Stacking Assembly of IC (Mosaic) Cube with Inductive Coupling for Exascale Memory Applications 

2025 IEEE 75th Electronic Components and Technology Conference (ECTC) 1324-1330 2025年5月27日  査読有り最終著者責任著者