2016年5月
High-efficiency CMOS push-pull power amplifier with multilayer center-tapped transformer
IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING
- ,
- ,
- ,
- 巻
- 11
- 号
- 3
- 開始ページ
- 384
- 終了ページ
- 386
- 記述言語
- 英語
- 掲載種別
- 研究論文(学術雑誌)
- DOI
- 10.1002/tee.22228
- 出版者・発行元
- WILEY-BLACKWELL
This paper describes the design of a push-pull power amplifier (PA) with a center-tapped transformer for transmitter applications on the 5.2-GHz band using 0.18m CMOS technology. The type of the proposed PA is based on a double-ended push-pull (DEPP) configuration. DEPP has a simple construction with only transistors and transformers. The PA has reverse-phased cascode-connected transistors. The proposed transformer has a multilayer structure and was designed using electromagnetic field simulation. To achieve high power added efficiency (PAE), we assumed the optimized output impedance technique with a tunable impedance antenna. The PA has 13.2 dB linearity gain, 14.9 dBm 1-dB compression point (P1dB), and 27.4% maximum PAE. (c) 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.
- リンク情報
- ID情報
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- DOI : 10.1002/tee.22228
- ISSN : 1931-4973
- eISSN : 1931-4981
- Web of Science ID : WOS:000374005700015