2012年
A stable chip-ID generating physical uncloneable function using random address errors in SRAM
International System on Chip Conference
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- 開始ページ
- 143
- 終了ページ
- 147
- 記述言語
- 英語
- 掲載種別
- 研究論文（国際会議プロシーディングス）
- DOI
- 10.1109/SOCC.2012.6398399
- 出版者・発行元
- IEEE
A stable chip-ID generating scheme using random failure bits in an SRAM array is proposed. Combining with a new screening test before shipping products, we realize high-tolerance against variability of operating condition. Measured data confirm that the stability and average of Hamming distance of 128 bit chip-ID achieve 100% and 63.7, respectively. The chip-ID generating time becomes less than 10us at 200 MHz operation. © 2012 IEEE.
- リンク情報
- ID情報
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- DOI : 10.1109/SOCC.2012.6398399
- ISSN : 2164-1676
- ISSN : 2164-1706
- DBLP ID : conf/socc/FujiwaraYTNOKN12
- SCOPUS ID : 84872574199