Masanori Hariyama

Profile Information

Affiliation: Professor, Graduate School of Information Sciences Department of Computer and Mathematical Sciences Computation Science and Systems Intelligent Integrated Systems, Tohoku University

Degree: Ph.D(Mar, 1997, Graduate School of Information Sciences, Tohoku University)

J-GLOBAL ID: 200901054127165069
researchmap Member ID: 1000221914

External link: http://db.tohoku.ac.jp/whois/e_detail/7bec791b67ea6dbe6a79073ec8cc0771.html

Research Areas

Informatics / Information theory / Intelligent Integrated Systems
Manufacturing technology (mechanical, electrical/electronic, chemical engineering) / Measurement engineering / Electronic Meqsurements

Awards

Papers

189

An FPGA Architecture for Text Search Using a Wavelet-Tree-Based Succinct-Data-Structure

Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama, Michitaka Kameyama

International Conference on Parallel and Distributed Processing Techniques and Applications(PDPTA), 354-359, Jul 28, 2105 Peer-reviewed
急性胆嚢炎診療の進歩、安全に患者を救うためには急性胆嚢炎は胆嚢亜全摘術施行へのリスクとなる

下田貢, 張山昌論, 鈴木修司

日本外科感染症学会雑誌, 19(1) 143-143, Oct, 2022
AIを用いた腹腔鏡下胆嚢摘出術困難症例に対するbailout surgeryの術式選択の可能性

下田貢, 張山昌論, 鈴木修司

日本外科学会定期学術集会抄録集, 122回 SF-5, Apr, 2022
FPGA-Accelerated Searchable Encrypted Database Management Systems for Cloud Services

Mitsuhiro Okada, Takayuki Suzuki, Naoya Nishio, Hasitha Muthumala Waidyasooriya, Masanori Hariyama

IEEE Transactions on Cloud Computing, 10(2) 1373-1385, Apr 1, 2022
Temporal and spatial parallel processing of simulated quantum annealing on a multicore CPU

Hasitha Muthumala Waidyasooriya, Masanori Hariyama

The Journal of Supercomputing, 78(6) 8733-8750, Apr, 2022
OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization

Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Hiroe Iwasaki, Daisuke Kobayashi, Yuya Omori, Ken Nakamura, Koyo Nitta, Kimikazu Sano

2022 IEEE 65TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS 2022), 2022
A Scalable Emulator for Quantum Fourier Transform Using Multiple-FPGAs With High-Bandwidth-Memory

Hasitha Muthumala Waidyasooriya, Hiroki Oshiyama, Yuya Kurebayashi, Masanori Hariyama, Masayuki Ohzeki

IEEE Access, 1-1, 2022
ナビゲーション手術の現状と今後肝切除術における超音波3D画像構築とナビゲーションシステムへの応用

下田貢, 張山昌論, 鈴木修司

日本臨床外科学会雑誌, 82(増刊) S96-S96, Oct, 2021
Highly-Parallel FPGA Accelerator for Simulated Quantum Annealing

Hasitha Muthumala Waidyasooriya, Masanori Hariyama

IEEE Transactions on Emerging Topics in Computing, 9(4) 2019-2029, Oct 1, 2021
Design space exploration for an FPGA-based quantum annealing simulator with interaction-coefficient-generators

Chia-Yin Liu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama

The Journal of Supercomputing, May 18, 2021 Peer-reviewed
腹腔鏡下胆嚢摘出術困難症例に対するBailout surgery移行判断のAIモデリング

下田貢, 張山昌論, 鈴木修司

日本外科学会定期学術集会抄録集, 121回 SF-4, Apr, 2021
A GPU-Based Quantum Annealing Simulator for Fully-Connected Ising Models Utilizing Spatial and Temporal Parallelism

Hasitha Muthumala Waidyasooriya, Masanori Hariyama

IEEE ACCESS, 8 67929-67939, 2020
Development of new software enabling automatic identification of the optimal anatomical liver resectable region, incorporating preoperative liver function

Mitsugi Shimoda, Masanori Hariyama, Yukio Oshiro, Shuji Suzuki

ONCOLOGY LETTERS, 18(6) 6639-6647, Dec, 2019 Peer-reviewed
OpenCL-based design of an FPGA accelerator for quantum annealing simulation

Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masamichi J. Miyama, Masayuki Ohzeki

JOURNAL OF SUPERCOMPUTING, 75(8) 5019-5039, Aug, 2019
Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability

Hasitha Muthumala Waidyasooriya, Masanori Hariyama

IEEE ACCESS, 7 53188-53201, 2019
Benchmarks for FPGA-Targeted High-Level-Synthesis

Hasitha Muthumala Waidyasooriya, Yasuaki Iimura, Masanori Hariyama

2019 SEVENTH INTERNATIONAL SYMPOSIUM ON COMPUTING AND NETWORKING (CANDAR 2019), 232-238, 2019
An FPGA accelerator for PatchMatch multi-view stereo using OpenCL

Shunsuke Tatsumi, Masanori Hariyama, Koichi Ito, Takafumi Aoki

Journal of Real-Time Image Processing, 1-13, Feb 15, 2018 Peer-reviewed
Implementation of an FPGA Accelerator for Text Search Using a Wavelet-Tree-Based Succinct-Data-Structure

Taisuke Ono, Hasitha Muthumala Waidyasooriya, Masanori Hariyama

13th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), 1-12, Jan 24, 2018 Peer-reviewed
A System for Estimating Optimal Resected Liver Regions Considering Practical Surgical Constraints.

Yaya Watanabe, Masanori Hariyama, Mitsugi Shimoda

2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)(ISPACS), 415-420, 2018 Peer-reviewed
Architecture of an FPGA-based heterogeneous system for code-search problems

Yuki Hiradate, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masaaki Harada

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 10776 146-155, 2018 Peer-reviewed

Misc.

106

最新の画像技術と手術 3D-CTシミュレーションから超音波3D画像を用いたナビゲーションシステムの構築

下田貢, 張山昌論, 大城幸雄, 鈴木修司

日本外科系連合学会誌, 44(3) 427-427, May, 2019
術前肝機能を考慮した最適肝切除領域自動抽出ソフトウエアの開発

下田貢, 張山昌論, 鈴木修司

日本外科学会定期学術集会抄録集, 118回 1656-1656, Apr, 2018
術前肝機能を考慮した最適肝切除領域自動抽出ソフトウエアの開発

下田貢, 張山昌論, 鈴木修司

日本外科学会定期学術集会(Web), 118th ROMBUNNO.PS‐035‐3 (WEB ONLY)-1656, Apr, 2018
OpenCL-Based FPGA Platform for FDTD Computation

116(56) 17-20, May 20, 2016
Evaluation of an OpenCL-Based FPGA Accelerator for Phase-Only Correlation

116(53) 103-108, May 19, 2016
Evaluation of an OpenCL-Based FPGA Platform for Particle Filter

116(53) 109-113, May 19, 2016
Design of an FPGA Platform for Stencil Computation Using OpenCL

116(53) 9-12, May 19, 2016
OpenCL-Based Design of an FPGA Accelerator for Phase-Only Correlation

28 377-382, Aug 3, 2015
An FPGA Architecture for Text Search Using a Wavelet-Tree-Based Succinct-Data-Structure

Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama, Michitaka Kameyama

International Conference on Parallel and Distributed Processing Techniques and Applications, 354-359, 2015 Peer-reviewed
Design of an FPGA-Based Accelerator for Shortest-Path Search over Large-Scale Graphs

TAKEI Yasuhiro, HARIYAMA Masanori, KAMEYAMA Michitaka

IEICE technical report, 114(75) 79-83, Jun 11, 2014
Highly-Parallel FPGA Accelerator for DNA Sequence Alignment Using the Burrows-Wheeler Algorithm

WAIDYASOORIYA Hasitha Muthumala, HARIYAMA Masanori, KAMEYAMA Michitaka

IEICE technical report, 114(75) 17-20, Jun 11, 2014
Platform and Mapping Methodology for Heterogeneous Multicore Processors

HARIYAMA Masanori, WAIDYASOORIYA Hasitha Muthumala, TAKEI Yasuhiro, KAMEYAMA Michitaka

Interdisciplinary Information Sciences, 18(2) 175-184, Dec 10, 2012
Computing Technologies for Human-Centered Real-World Intelligent Systems

HARIYAMA Masanori, KAMEYAMA Michitaka

IEICE technical report. Image engineering, 112(248) 31-33, Oct 11, 2012
Low-Power Heterogeneous Platform for High Performance Computing and Its Application to 2-D FDTD Computation

HARIYAMA Masanori, HASITHA Muthumalawaidyasoority, TAKEI Yasuhiro, KAMEYAMA Michitaka

IEICE technical report, 112(203) 89-93, Sep 18, 2012
An Evaluation of An FPGA Based on Synchronous/Asynchronous Hybrid Architecture

KOMATSU Yoshiya, HARIYAMA Masanori, ISHIHARA Shota, TSUCHIYA Ryoto, KAMEYAMA Michitaka

Technical report of IEICE. ICD, 111(388) 93-96, Jan 19, 2012
An Evaluation of An FPGA Based on Synchronous/Asynchronous Hybrid Architecture

2012(17) 1-4, Jan 12, 2012
Dual-Rail/Single-Rail Hybrid Logic Design for High-Performance Asynchronous Circuit

Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama

IEEE International Symposium on Circuits and Systems, 3017-3020, 2012
グラフ構造解析に基づく肝臓血管の自動抽出

尾形吉隆, 張山昌論, 亀山充隆, 下田貢

電気関係学会東北支部連合大会講演論文集(CD-ROM), 2012 67-67, 2012
FPGA Platform for Heterogeneous Multicore Processors with MIMD-ALU-array-type Dynamically Reconfigurable Accelerators

TAKEI Yasuhiro, WAIDYASOORIYA Hasitha Muthumala, HARIYAMA Masanori, KAMEYAMA Michitaka

Technical report of IEICE. ICD, 111(258) 73-76, Oct 17, 2011
Simultaneous Optimization of a CDFG Structure and a Schedule Based on Super-node Representation

HIRATA Akira, WAUDYASOORIYA Hasitha MUTHUMALA, HARIYAMA Masanori, KAMEYAMA Michitaka

Technical report of IEICE. ICD, 111(258) 101-105, Oct 17, 2011

Books and Other Publications

Design of FPGA-Based Computing Systems with OpenCL

Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Kunio Uchiyama

Nov, 2017
FPGAの原理と構成

張山昌論 (Role: Joint author, 255頁〜272頁)

オーム社, Mar, 2016
Emerging Trends in Image Processing, Computer Vision, and Pattern Recognition

Masanori Hariyama, Mitsugi Shimoda (Role: Joint author, Chapter 23(Automatic estimation of a resected liver region using a tumor domination ratio))

Morgan Kaufmann Publishers, Jan, 2015
Towards Green ICT

M.Kameyama, M.Hariyama (Role: Joint author, Chapter 17, pp.265-274, "Interconnect-Aware High-Level Design Methodologies for Low-Power VLSIs")

River Publishers Series in Communications, Jul, 2010
映像情報メディア工学大事典

張山昌論

オーム社, Jun, 2010 (ISBN: 9784274208690)

Presentations

FPGAを用いたヘテロジニアスマルチコアプロセッサのプラットフォーム開発

電子情報通信学会集積回路研究会主催第２回アクセラレーション技術発表討論会, Sep 10, 2010
リアルワールド知能システムとヘテロジニアスマルチコアアーキテクチャの展望

第8回 SuperH フォーラム, Sep 4, 2009

Professional Memberships

Research Projects

細胞社会は互いのコミュニケーションをどのようにとっているか：複雑系の視点

科学研究費助成事業, 基盤研究(C), 日本学術振興会, Apr, 2021 - Mar, 2024

岸本聡子, 井上健一, 張山昌論
Custom Accelerators for Quantum-Annealing-Assisted Material Informatics

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, Apr, 2020 - Mar, 2024
Establishment of Effective Science Education during School Age utilizing Brain Science-based Methods by a Medical Doctor and a Psychologist

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (C), Japan Society for the Promotion of Science, Apr, 2021 - Mar, 2022
Development of epigenomic markers that enable to perform early assessment and intervention for neurodevelopmental disorders

Grants-in-Aid for Scientific Research, Grant-in-Aid for Challenging Research (Exploratory), Japan Society for the Promotion of Science, Jun, 2018 - Mar, 2022
Intraoperative planning and navigation based on three-dimensional image processing combining ultrasound and CT

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, Apr, 2016 - Mar, 2020

Shimoda Mitsugi
Development of Highly-reliable and Low-power reconfigurable VLSI Based on Asynchronous architecture and Non-volatile memory

Grants-in-Aid for Scientific Research, Grant-in-Aid for Challenging Exploratory Research, Japan Society for the Promotion of Science, Apr, 2016 - Mar, 2018

Masanori Hariyama
Development of Heterogeneous-Computing Platform with Custom Accelerators for Embedded HPC Applications

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, Apr, 2012 - Mar, 2016

Hariyama Masanori, Waidyasooriya Hasitha Muthumala
Development of Surgery Navigation System Based on Real-time Intelligent Image Processing and Augmented Reality

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (C), Japan Society for the Promotion of Science, Apr, 2012 - Mar, 2015

SHIMODA Mitsugi, HARIYAMA Masanori
Low-Power FPGA Based on Fine-grained Autonomous Supply-Voltage Control

Grants-in-Aid for Scientific Research, Grant-in-Aid for Young Scientists (B), Japan Society for the Promotion of Science, 2009 - 2011

HARIYAMA Masanori
Optimal VLSI Design for a Highly-Safe Intelligent Vehicle Based on a System Integration Theory

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 2005 - 2007

KAMEYAMA Michitaka, HARIYAMA Masanori
リアルワールド知能システム用超高速ステレオビジョンVLSIプロセッサの開発

科学研究費助成事業, 若手研究(B), 日本学術振興会, 2004 - 2006

張山昌論
リアルワールド応用低消費電力リコンフィギャラブルVLSIプロセッサの開発

科学研究費助成事業, 若手研究(B), 日本学術振興会, 2001 - 2002

張山昌論
Development of VLSI Processor Chip Family for Highly-Safe Intelligent Vehicles Based on Optimal Design Mythologies

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 2000 - 2002

KAMEYAMA Michitaka, HARIYAMA Masanori
Reconfigurable Architecture and its applications

The Other Research Programs, Apr, 2000
Implementation of a One-Transistor Multiple-Valued Content-Addressalbe Memory and Its Application

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B)., Japan Society for the Promotion of Science, 1997 - 2000

HANYU Takahiro, KAMEYAMA Michitaka
面積・時間積最小化に基づく最高性能知能集積システム用VLSIプロセッサの開発

科学研究費助成事業, 奨励研究(A), 日本学術振興会, 1998 - 1999

張山昌論
Development of a Chip Family for Ultra-Highly-Parallel Multiple-Valued Integrated Circuits and Its Applications

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 1997 - 1999

KAMEYAMA Michitaka, HARIYAMA Masanori, HANYU Takahiro
High-Level Synthesis of High-Performance VLSI Processors for Intelligent Integrated System

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 1997 - 1999

KAMEYAMA Michitaka, HARIYAMA Masanori, HANYU Takahiro
Highly-Safe Intelligent Integrated System

Aug, 1993
Robot Electronics System

Aug, 1993

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