Hideo FUJIWARA

J-GLOBAL         Last updated: Sep 10, 2019 at 20:05
 
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Name
Hideo FUJIWARA
URL
http://hideo.fujiwaralab.net/
Affiliation
Osaka Gakuin University
Section
Faculty of Informatics
Job title
Professor
Degree
Ph.D.(Osaka University)
Other affiliation
Professor Emeritus, Nara Institute of Science and Technology

Profile

Technical Biography
Hideo Fujiwara received the B.E., M.E., and Ph.D. degrees in electronic engineering from Osaka University, Osaka, Japan, in 1969, 1971, and 1974, respectively. He was with Osaka University from 1974 to 1985, Meiji University from 1985 to 1993, Nara Institute of Science and Technology (NAIST) from 1993 to 2011, and joined Osaka Gakuin University in 2011. Presently he is Professor Emeritus of NAIST and a Professor at the Faculty of Informatics, Osaka Gakuin University, Osaka, Japan.
His research interests are logic design, digital systems design and test, VLSI CAD and fault tolerant computing, including high-level/logic synthesis for testability, test synthesis, design for testability, built-in self-test, test pattern generation, parallel processing, and computational complexity. He has published over 400 papers in refereed journals and conferences, and nine books including the book from the MIT Press (1985) entitled “Logic Testing and Design for Testability.” He received the IECE Young Engineer Award in 1977, IEEE Computer Society Certificate of Appreciation Awards in 1991, 2000 and 2001, Okawa Prize for Publication in 1994, IEEE Computer Society Meritorious Service Awards in 1996 and 2005, IEEE Computer Society Continuing Service Award in 2005, and IEEE Computer Society Outstanding Contribution Award in 2001 and 2009.
He served as an Editor of the IEEE Trans. on Computers (1998-2002), Journal of Electronic Testing: Theory and Application (1989-2004), Journal of Circuits, Systems and Computers (1989-2004), VLSI Design: An Application Journal of Custom-Chip Design, Simulation, and Testing (1992-2005), and several guest editors of special issues of IEICE Transactions of Information and Systems. Dr. Fujiwara is a life fellow of the IEEE, a Golden Core member of the IEEE Computer Society, a fellow of the IEICE (the Institute of Electronics, Information and Communication Engineers of Japan) and a fellow of the IPSJ (the Information Processing Society of Japan).

Research Interests

 
 

Research Areas

 
 

Academic & Professional Experience

 
1974
 - 
1985
Osaka University, Faculty of Engineering,
 
 
   
 
Assistant Professor
 
1981
   
 
Univ. of Waterloo, Visiting Research Assistant
 
 
   
 
Professor
 
1984
   
 
McGill University, Visiting Associate Professor
 
1985
 - 
1990
Meiji University, Faculty of Eng., Associate
 
 
   
 
Professor
 
1990
 - 
1993
Meiji University, Faculty of Science and
 
 
   
 
Engineering, Professor
 
1993
 - 
2011
Nara Institute of Science and Technology,
 

Education

 
 
 - 
1974
Depantment of Electronic Engineering, Graduate School, Division of Engineering, Osaka University
 
 
 - 
1969
Depantment of Electiomic Engineering, Faculty of Engineering, Osaka University
 

Committee Memberships

 
1986
 - 
1991
IEEE  Far East Editor, IEEE Design and Test of Computers
 
1988
 - 
1992
IEEE  Asian Vice Chair, IEEE International Test Conference
 
1990
 - 
1992
IEICE  Editor, IEICE Trans. on Information and Systems, IEICE Japan, May 1990 - Dec. 1992
 
1992
 - 
1993
IEICE  Chair, Technical Group on VLSI Design Technology
 
1992
 - 
2000
IEEE,Computer Socciety,Test Technology Technical Council  Vice Chair, IEEE TTTC Awards Committee
 
1993
 - 
1996
IEICE  Advisory Member, IEICE Editorial Board
 
1993
 - 
Today
IEICE  Advisory Member, IEICE Trans. on Information and Systems
 
1995
 - 
1997
IEICE  Chair, Technical Group on Fault Tolerant Systems
 
1998
 - 
2002
IEEE  Associate Editor, IEEE Transactions on Computers
 
2001
 - 
2004
IEEE, Computer Society, Test Technology Technical Council  Chair, IEEE Asian Test Symposium Steering Committee
 
2003
 - 
2006
IEEE, Computer Society, Test Technology Technical Council  IEEE WRTLT Steering Committee Chair
 
2004
 - 
2008
IEEE,Computer Society, Test Technology Technical Council  Chair, Asia and Pacific Regional TTTC, IEEE Computer Society
 
2003
 - 
2008
IEEE  Board Member of IEEE Kansai Section (in Japan, Region 10)
 

Awards & Honors

 
2016
ATS Most Contribution Author Award, IEEE Computer Society TTTC
 
2016
Outstanding Contribution Award, IEEE Computer Society TTTC
 
2012
Life Fellow, IEEE
 
2001
IECE Young Engineer Award
 
20011977
1989
IEEE Fellow Award
 
1991
IEEE Computer Society Certificate of Appreciation Award
 
1994
The Okawa Publications Prize
 
1996
IEEE Computer Society Meritorious Service Award
 
1997
IEEE Computer Society Golden Core Member Award
 
2000
IEEE Computer Society Certificate of Appreciation Award
 
2001
IEICE Fellow
 
2001
IEEE Computer Society Certificate of Appreciation Award
 
2001
IEEE Computer Society Outstanding Contribution Award
 
2002
EICE ISS 2001 Year Paper Award
 
2004
IPSJ Fellow
 
2004
IEEE WRTLT 2003 Best Paper Award
 
2004
IEEE ATS'02 Best Paper Award (IEEE Asian Test Symposium 2002)
 
2005
IEEE Computer Society Continuing Service Award
 
2005
IEEE Computer Society Meritorious Service Award
 
2006
IEEE DELTA'06 Best Paper Award (Third IEEE International Workshop on Electronic Design, Test & Applications, DELTA 2006)
 
2006
IEEE WRTLT'05 Best Paper Award (IEEE Workshop on RTL and High Level Testing 2005)
 
2008
IEEE WRTLT'07 Best Paper Award (IEEE Workshop on RTL and High Level Testing 2007)
 
2009
IEEE Computer Society Outstanding Contribution Award
 
2009
IEEE WRTLT'08 Best Paper Award (IEEE Workshop on RTL and High Level Testing 2008)
 
2011
IEEE Kansai Section Medal
 
2011
IEEE Life Fellow
 

Misc

 
Number of publications till 2018 = 174 journal papers + 251 conference papers
till 2018
   2019
Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing
Dong Xiang, Krishnendu Chakrabarty, and Hideo Fujiwara,
ACM Trans. on Design Automation of Electronic Systems   Vol. 23(No. 6)    Dec 2018   [Refereed]
Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents
Hideo Fujiwara and Katsuya Fujiwara
IEICE Trans. on Inf. and Syst.   Vol. E100-D(No.9) 2232-2236   Sep 2017   [Refereed]
A Unified Test and Fault-Tolerant Multicast Solution for Network-on-Chip Designs
Dong Xiang, Krishnendu Chakrabarty, and Hideo Fujiwara
IEEE International Test Conference 2016      Nov 2016   [Refereed]
Realization of SR-Equivalents Using Generalized Shift Registers for Secure Scan Design
Hideo Fujiwara and Katsuya Fujiwara
IEICE Trans. on Inf. and Syst.   Vol. E99-D(No. 8) 2182-2185   Aug 2016   [Refereed]
Jun Nishimaki, Toshinori Hosokawa and Hideo Fujiwara
21st IEEE European Test Symposium (ETS'16)      May 2016   [Refereed]
Hideo Fujiwara and Katsuya Fujiwara
IEICE Trans. on Inf. and Syst.   Vol. E99-D(No. 4)    Apr 2016   [Refereed]
Dong Xiang, Krishnendu Chakrabarty, and Hideo Fujiwara
IEEE Trans. on Computers      2016   [Refereed]
Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa and Hideo Fujiwara
IEEE the 24th Asian Test Symposium   37-42   Nov 2015   [Refereed]
A Scheduling Method for Hierarchical Testability Using Results of Test Environment Generation
Jun Nishimaki, Toshinori Hosokawa and Hideo Fujiwara
15th IEEE Workshop on RTL and High Level Testing (WRTLT'14)      Nov 2015   [Refereed]
Hideo Fujiwara and Katsuya Fujiwara
IEICE Trans. on Inf. and Syst.   Vol. E98-D(10) 1852-1855   Oct 2015   [Refereed]
Debesh K. Das and Hideo Fujiwara
Journal of Electronic Testing: Theory and Applications (JETTA)   Vol. 31(3) 321-327   Jun 2015   [Refereed]
A Binding Method for Hierarchical Testability Using Results of Test Environment Generation
Jun Nishimaki, Toshinori Hosokawa and Hideo Fujiwara
2nd Workshop on Design Automation for Understanding Hardware Designs      Mar 2015   [Refereed]
A Controller Augmentation Method to Generate Easily Testable Functional k-Time Expansion Models for Data Path Circuits
Yusuke Kodama, Jun Nishimaki, Tetsuya Masuda, Toshinori Hosokawa, and Hideo Fujiwara
14th IEEE Workshop on RTL and High Level Testing (WRTLT'13)      Nov 2013   [Refereed]
Functional Unit and Register Binding Methods for Hierarchical Testability
Jun Nishimaki, Toshinori Hosokawa, and Hideo Fujiwara
14th IEEE Workshop on RTL and High Level Testing (WRTLT'13)      Nov 2013   [Refereed]
Dong Xiang, Gang Liu, Krishnendu Chakrabarty, and Hideo Fujiwara
21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)      Oct 2013
Katsuya Fujiwara and Hideo Fujiwara
IEICE Trans. on Inf. and Syst.   Vol. E96-D(No. 5) 1125-1133   May 2013   [Refereed]
Katsuya Fujiwara, Hideo Fujiwara, and Hideo Tamamoto
IPSJ Trans. on System LSI Design Methodology   Vol. 6 27-33   Feb 2013   [Refereed]
Michiko Inoue, Akira Taketani, Tomokazu Yoneda, and Hideo Fujiwara
IEICE Trans. on Inf. and Syst.   Vol. E95-D(12) 3001-3009   Dec 2012   [Refereed]
WAGSR: Web Application for Generalized Feed Forward Shift Registers
Katsuya Fujiwara and Hideo Fujiwara
13th IEEE Workshop on RTL and High Level Testing (WRTLT'12)      Nov 2012   [Refereed]
The Past and Future of WRTLT
Yinghua Min and Hideo Fujiwara
13th IEEE Workshop on RTL and High Level Testing (WRTLT'12)      Nov 2012   [Refereed]
Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, and Hideo Fujiwara
IEEE Trans. on Very Large Scale Integration Systems   Vol. 20(No.11) 1951-1959   Nov 2012   [Refereed]
Taavi Viilukas, Anton Karputkin, Jaan Raik, Maksim Jenihhin, Raimund Ubar, and Hideo Fujiwara
Journal of Electronic Testing: Theory and Applications (JETTA)   Vol. 28(No. 4) 511-521   2012   [Refereed]
A Binding Method for Hierarchical Testing Using Results of Test Environment Generation
Hiroaki Fujiwara, Toshinori Hosokawa, Ryoichi Inoue, and Hideo Fujiwara
12th IEEE Workshop on RTL and High Level Testing (WRTLT'11)      Nov 2011   [Refereed]
Built-in Self-Test for Functional Register-Transfer Level using Assignment Decision Diagram
Norlina Paraman, Chia Yee Ooi, Ahmad Zuri Sha'Ameri, and Hideo Fujiwara
12th IEEE Workshop on RTL and High Level Testing (WRTLT'11)   9-15   Nov 2011   [Refereed]
SR-Quasi-Equivalents: Yet Another Approach to Secure and Testable Scan Design
Katsuya Fujiwara, Hideo Fujiwara, and Hideo Tamamoto
12th IEEE Workshop on RTL and High Level Testing (WRTLT'11)      Nov 2011   [Refereed]
Chia Yee Ooi and Hideo Fujiwara
 Journal of Electronic Testing: Theory and Applications (JETTA)   Vol. 27(5) 583-598   Oct 2011   [Refereed]
Tomokazu Yoneda, Keigo Hori, Michiko Inoue, and Hideo Fujiwara
2011 IEEE International Test Conference      Sep 2011   [Refereed]
Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, and Hideo Fujiwara
2011 IEEE European Test Symposium      2011
May 2011.
Marie Engelene J. Obien, Satoshi Ohtake, and Hideo Fujiwara
2011 IEEE European Test Symposium      2011
May 2011.
Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Hideo Fujiwara, and Raimund Ubar
2011 IEEE European Test Symposium      2011
May 2011.
Hideo Fujiwara, Katsuya Fujiwara, and Hideo Tamamoto
16th Asia and South Pacific Design Automation Conference   818-823   2011
Jan. 2011.
Katsuya Fujiwara, Hideo Fujiwara, and Hideo Tamamoto
IEICE Trans. on Inf. and Syst.   E94-D(7) 1430-1439   2011
July 2011
Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, and Hideo Fujiwara
Journal of Electronic Testing: Theory and Applications   27(2) 99-108   2011
April 2011
Marie Engelene Jimenez Obien, Satoshi Ohtake, and Hideo Fujiwara
IEICE Trans. on Inf. and Syst.   E94-D(1) 104-113   2011
Jan. 2011
Fawnizu Azmadi Hussin, Thomas Edison Chua Yu, Tomokazu Yoneda, and Hideo Fujiwara,
2010 Asia Pacific Conference on Circuits and Systems      2010
Dec. 2010
An Approach for Verification Assertions Reuse in RTL Test Pattern Generation
Maksim Jenihhin, Jaan Raik, Hideo Fujiwara, Raimund Ubar, and Taavi Viilukas
11th IEEE Workshop on RTL and High Level Testing   107-110   2010
Dec. 2010
Functional Fault Model for Micro Operation Faults of High Correlation with Stuck-At FaultsStuck-At Faults
Chia Yee Ooi and Hideo Fujiwara
11th IEEE Workshop on RTL and High Level Testing   139-144   2010
Dec. 2010
SREEP-2: SR-Equivalent Generator for Secure and Testable Scan Design
Katsuya Fujiwara, Hideo Fujiwara, and Hideo Tamamoto
11th IEEE Workshop on RTL and High Level Testing   7-12   2010
Dec. 2010
Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, and Hideo Fujiwara
Proc. of IEEE the 19th Asian Test Symposium   371-374   2010
Dec. 2010
Tomokazu Yoneda, Michiko Inoue, Akira Taketani, and Hideo Fujiwara
Proc. of IEEE the 19th Asian Test Symposium   13-318   2010
Dec. 2010.
Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, and Hideo Fujiwara
Proc. of IEEE the 19th Asian Test Symposium   206-211   2010
Dec. 2010.
Alodeep Sanyal, Krishnendu Chakrabarty, Mahmt Yilmaz, and Hideo Fujiwara
2010 IEEE International Test Conference      2010
Nov. 2010
Marie Engelene J. Obien, Satoshi Ohtake, and Hideo Fujiwara
2010 IEEE International Test Conference      2010
2010 IEEE International Test Conference
Marie Engelene Jimenez Obien, Satoshi Ohtake, and Hideo Fujiwara,
IEEE Int. Symp. on Communications and Information Technologies      2010
Oct. 2010
Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, and Hideo Fujiwara
IEEE International On-Line Testing Symposium   21-26   2010
July 2010
Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara
ACM Great Lake Symposium on VLSI   73-78   2010
May 2010
Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, and Hideo Fujiwara
2010 IEEE European Test Symposium      2010
May 2010
Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara
2010 IEEE European Test Symposium      2010
May 2010
Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara
8th IEEE VLSI Test Symposium   188-193   2010
April 2010
Satoshi Ohtake, Hiroshi Iwata, and Hideo Fujiwara
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems   197-200   2010
April 2010
Katsuya Fujiwara, Hideo Fujiwara, Marie Engelene J. Obien, and Hideo Tamamoto
13th IEEE International Symposium on Design and Diagnosis of Electronic Circuits and Systems   193-196   2010
April 2010
Satoshi Ohtake, Naotsugu Ikeda, Michiko Inoue, and Hideo Fujiwara
5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era      2010
March 2010.
Hiroshi Iwata, Satoshi Ohtake, and Hideo Fujiwara
The 5th IEEE International Symposium on Electronic Design, Test & Applications   20-25   2010
Jan. 2010
Hideo Fujiwara and Marie E. J. Obien
15th Asia and South Pacific Design Automation Conference   413-418   2010
Jan. 2010
Optimizing Delay Test Quality with a Limited Size of Test Set
Michiko Inoue, Akira Taketani, Tomokazu Yoneda, and Hideo Fujiwara
First IEEE International Workshop on Reliability Aware System Design and Test   46-51   2010
Jan. 2010
Raghavendra Adiga, Arpit Gandhi, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, and Adit D. Singh
23rd Internaional Conference on VLSI Design   293-398   2010
Jan. 2010
An Approach for Verification Assertions Reuse in RTL Test Pattern Generation
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Taavi Viilukas, and Hideo Fujiwara
Journal of Shanghai Normal University   39(5) 441-447   2010
Oct. 2010
Enumeration and Synthesis of Shift Register Equivalents for Secure Scan Design
Katsuya Fujiwara, Hideo Fujiwara, Marie E. J. Obien, and Hideo Tamamoto
IEICE Trans. on Inf. and Syst.   J93-D(11) 2426-2436   2010
Nov. 2010
A New Class of Easily Testable Assignment Decision Diagram
Norlina Paraman, Chia Yee Ooi, Ahmad Zuri Sha'ameri, and Hideo Fujiwara
Malayaisan Journal Computer Science   23(1) 1-17   2010
Hiroshi Iwata, Satoshi Ohtake, and Hideo Fujiwara
IEICE Transactions on Information and Systems   E93-D(7) 1857-1865   2010
July 2010
Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, and Hideo Fujiwara
IEICE Trans. on Inf. and Syst.   E93-D(6) 1549-1559   2010
June 2010
Hongxia Fang, Krishnendu Chakrabarty, and Hideo Fujiwara
Journal of Electronic Testing: Theory and Applications   26(2) 151-164   2010
April 2010
Ryoichi Inoue, Toshinori Hosokawa, and Hideo Fujiwara
IEICE Transactions on Information and Systems   E93-D(1) 24-32   2010
Ryoichi Inoue, Toshinori Hosokawa, and Hideo Fujiwara
IEICE Transactions on Information and Systems   E93-D(1) 24-32   2010
227 conference papers
   2010
till 2010
158 journal papers
   2010
till 2010
Observation-Point Selection at Register-Transfer Level to Increase Defect Coverage for Functional Test Sequences
Hongxia Fang, Krishnendu Chakrabarty and Hideo Fujiwara
10th IEEE Workshop on RTL and High Level Testing (WRTLT'09)      2009
Scan Cell Reordering to Minimize Peak Power during Scan Testing of SoC
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh and Hideo Fujiwara
10th IEEE Workshop on RTL and High Level Testing (WRTLT'09)      2009
Path-based Resource Binding to Reduce Delay Fault Test Cost
Michiko Inoue, Satoshi Ohtake, Yu-ichi Uemoto and Hideo Fujiwara
10th IEEE Workshop on RTL and High Level Testing (WRTLT'09)      2009
A DFT Method for Functional Scan at RTL
Marie E. J. Obien and Hideo Fujiwara
10th IEEE Workshop on RTL and High Level Testing (WRTLT'09)      2009
Hongxia Fang, Krishnendu Chakrabarty and Hideo Fujiwara
IEEE International High Level Design Validation and Test Workshop 2009 (IEEE HLDVT 2009)      2009
A Response Compactor for Extended Compatibility Scan Tree Construction
Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, and Hideo Fujiwara
Proc. IEEE 8th International Conference on ASIC (ASICON2009)      2009
F-Scan: An Approach to Functional RTL Scan for Assignment Decision Diagrams
Marie Engelene J. Obien and Hideo Fujiwara
Proc. IEEE 8th International Conference on ASIC (ASICON2009)      2009
A Circuit Failure Prediction Mechanism (DART) for High Field Reliability
Yasuo Sato, Seiji Kajihara, Yukiya Mimura, Tomokazu Yoneda, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara
Proc. IEEE 8th International Conference on ASIC (ASICON2009)      2009
Acceleration by Contention for Shared Memory Mutual Exclusion Algorith
Michiko Inoue, Tsuyoshi Suzuki and Hideo Fujiwara
Proc. 23rd International Symposium on Distributed Computing (DISC 09)      2009
Test Generation and DFT Based on Partial Thru Testability
Nobuya Oka, Chia Yee Ooi, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
2009 IEEE European Test Symposium      2009
Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara
2009 IEEE European Test Symposium   143-148   2009
Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
IEEE VTS'09 (27th VLSI Test Symposium)   71-76   2009
Unsensitizable Path Identification at RTL Using High-Level Synthesis Information
Satoshi Ohtake, Naotsugu Ikeda, Michiko Inoue and Hideo Fujiwara
16th IEEE International Test Synthesis Workshop (ITSW 2009)      2009
Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara
14th Asia and South Pacific Design Automation Conference (ASP-DAC 2009)   793-798   2009
Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
14th Asia and South Pacific Design Automation Conference (ASP-DAC 2009)   660-665   2009
Test Generation for Sequential Circuits with Partial Thru Testability
Nobuya Oka, ChiaYee Ooi, Hideyuki Ichihara, Tomoo Inoue, and Hideo Fujiwara
IEICE Transactions on Information and Systems,   J92-D(12)    2009
Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, and Hideo Fujiwara
IEICE Transactions on Information and Systems   E91-D(10) 2440-2448   2008
Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, and Chia Yee Ooi
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems   27(9) 1535-1544   2008
Fawnizu Azmadi Hussin, Tomokazu Yoneda, and Hideo Fujiwara
IEICE Transactions on Information and Systems   E91-D(7) 2008-2017   2008
Fawnizu Azmadi Hussin, Tomokazu Yoneda, and Hideo Fujiwara
IEICE Transactions on Information and Systems   E91-D(7) 1999-2007   2008
Dong Xiang, Yang Zhao, Krishnendu Chakrabarty, and Hideo Fujiwara
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems   27(6) 999-1012   2008
Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, and Hideo Fujiwara
IEICE Transactions on Information and Systems   E91-D(3) 807-814   2008
Masato Nakazato, Michiko Inoue, Satoshi Ohtake, and Hideo Fujiwara
IEICE Transactions on Information and Systems   E91-D(3) 763-770   2008
Tomokazu Yoneda, Kimihiko Masuda, and Hideo Fujiwara
IEICE Transactions on Information and Systems   E91-D(3) 747-755   2008
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, and Hideo Fujiwara
IEICE Transactions on Information and Systems   E91-D(3) 736-746   2008
Tsuyoshi Iwagaki, Satoshi Ohtake, and Hideo Fujiwara
IFIP International Federation for Information Processing   249 301-306   2008
An approach to RTL-GL path mapping based on functional equivalence
Hiroshi Iwata, Satoshi Ohtake and Hideo Fujiwara
9th IEEE Workshop on RTL and High Level Testing   63-68   2008
RT-level identification of potentially testable initialization faults
Jaan Raik, Hideo Fujiwara, and Anna Krivenko
9th IEEE Workshop on RTL and High Level Testing   57-62   2008
A new class of easily testable assignment decision diagram
Norlina Paraman, Chia Yee Ooi, Ahmad Zuri Sha'ameri and Hideo Fujiwara
9th IEEE Workshop on RTL and High Level Testing   51-56   2008
Enhancement of test environment generation for assignment decision diagrams
Hideo Fujiwara, Chia Yee Ooi and Yuki Shimizu
9th IEEE Workshop on RTL and High Level Testing   45-50   2008
A reconfigurable wrapper design for multi-clock domain cores
Takashi Yoshida, Tomokazu Yoneda and Hideo Fujiwara
9th IEEE Workshop on RTL and High Level Testing   13-18   2008
Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, and Hideo Fujiwara
Proc. of IEEE the 17th Asian Test Symposium   125-130   2008
Ryoichi Inoue, Toshinori Hosokawa, and Hideo Fujiwara
Proc. of IEEE the 17th Asian Test Symposium   27-34   2008

Books etc

 
9 books
2008   
till 2008
Basic Logic and Mathematics of Switching Theory
Ohm-Sha   1980   
Fault Diagnosis of Digital Circuits
Kogakutosho   1983   
Logic Testing and Design for Testability
MIT Press   1985   
Introduction to Computer Design
Kogakutosho   1998   
Design and Test of Computers
Kogakutosho   1990   
Architecture and Design of Fault Tolerant Systems
Makishoten   1991   
Design and Test of Digital Systems
Kogakutosho   2004   

Works

 
STARC (Semiconductor Technology Academic Research Center) "Research on High Level Synthesis of High Performance and High Testability VLSI Circuits"
1997 - 2000
STARC (Semiconductor Technology Academic Research Center) "Research and Development on V-Core Based Design for Testability Technology"
2000 - 2002
TAO (Telecommunications Advancement Organization of Japan) "Research on High-Speed and High-Reliable Satellite Communication Systems"
1996 - 1998
STARC (Semiconductor Technology Academic Research Center) "Research on Instruction-level Self-test and Design-for-testability for Processors"
2003 - 2005
RSTARC (Semiconductor Technology Academic Research Center) "Research on test time and yield loss reduction through false path indentification and its propagation from behavioral to structural representations"
2006 - 2008

Research Grants & Projects

 
Study on Design Automation of Computers
Study on Fault Tolerant Computers
Study on Hardware/Software Codesign

Patents

 
Mothod of design for testalility and method of test segeuence generation
6,292,915
Testable Integrated Cirauit,Integrated Ciram't Design-for-Testbility Method,and Compiter-Readable Medium Storing A Program for INplementing The Design-for-Testability Meitod
6334200B1
Integrated Circuits and its Design Method
09/699478