Hideo FUJIWARA

J-GLOBAL         Last updated: Feb 7, 2019 at 10:19
 
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Name
Hideo FUJIWARA
URL
http://hideo.fujiwaralab.net/
Affiliation
Osaka Gakuin University
Section
Faculty of Informatics
Job title
Professor
Degree
Ph.D.(Osaka University)
Other affiliation
Professor Emeritus, Nara Institute of Science and Technology

Profile

Technical Biography
Hideo Fujiwara received the B.E., M.E., and Ph.D. degrees in electronic engineering from Osaka University, Osaka, Japan, in 1969, 1971, and 1974, respectively. He was with Osaka University from 1974 to 1985, Meiji University from 1985 to 1993, Nara Institute of Science and Technology (NAIST) from 1993 to 2011, and joined Osaka Gakuin University in 2011. Presently he is Professor Emeritus of NAIST and a Professor at the Faculty of Informatics, Osaka Gakuin University, Osaka, Japan.
His research interests are logic design, digital systems design and test, VLSI CAD and fault tolerant computing, including high-level/logic synthesis for testability, test synthesis, design for testability, built-in self-test, test pattern generation, parallel processing, and computational complexity. He has published over 400 papers in refereed journals and conferences, and nine books including the book from the MIT Press (1985) entitled “Logic Testing and Design for Testability.” He received the IECE Young Engineer Award in 1977, IEEE Computer Society Certificate of Appreciation Awards in 1991, 2000 and 2001, Okawa Prize for Publication in 1994, IEEE Computer Society Meritorious Service Awards in 1996 and 2005, IEEE Computer Society Continuing Service Award in 2005, and IEEE Computer Society Outstanding Contribution Award in 2001 and 2009.
He served as an Editor of the IEEE Trans. on Computers (1998-2002), Journal of Electronic Testing: Theory and Application (1989-2004), Journal of Circuits, Systems and Computers (1989-2004), VLSI Design: An Application Journal of Custom-Chip Design, Simulation, and Testing (1992-2005), and several guest editors of special issues of IEICE Transactions of Information and Systems. Dr. Fujiwara is a life fellow of the IEEE, a Golden Core member of the IEEE Computer Society, a fellow of the IEICE (the Institute of Electronics, Information and Communication Engineers of Japan) and a fellow of the IPSJ (the Information Processing Society of Japan).

Research Interests

 
 

Research Areas

 
 

Academic & Professional Experience

 
1974
 - 
1985
Osaka University, Faculty of Engineering,
 
 
   
 
Assistant Professor
 
1981
   
 
Univ. of Waterloo, Visiting Research Assistant
 
 
   
 
Professor
 
1984
   
 
McGill University, Visiting Associate Professor
 

Education

 
 
 - 
1974
Depantment of Electronic Engineering, Graduate School, Division of Engineering, Osaka University
 
 
 - 
1969
Depantment of Electiomic Engineering, Faculty of Engineering, Osaka University
 

Committee Memberships

 
1986
 - 
1991
IEEE  Far East Editor, IEEE Design and Test of Computers
 
1988
 - 
1992
IEEE  Asian Vice Chair, IEEE International Test Conference
 
1990
 - 
1992
IEICE  Editor, IEICE Trans. on Information and Systems, IEICE Japan, May 1990 - Dec. 1992
 
1992
 - 
1993
IEICE  Chair, Technical Group on VLSI Design Technology
 
1992
 - 
2000
IEEE,Computer Socciety,Test Technology Technical Council  Vice Chair, IEEE TTTC Awards Committee
 

Awards & Honors

 
2012
Life Fellow, IEEE
 
2001
IECE Young Engineer Award
 
20011977
1989
IEEE Fellow Award
 
1991
IEEE Computer Society Certificate of Appreciation Award
 
1994
The Okawa Publications Prize
 

Misc

 
Number of publications till 2018 = 174 journal papers + 251 conference papers
till 2018
   2019
Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing
Dong Xiang, Krishnendu Chakrabarty, and Hideo Fujiwara,
ACM Trans. on Design Automation of Electronic Systems   Vol. 23(No. 6)    Dec 2018   [Refereed]
Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents
Hideo Fujiwara and Katsuya Fujiwara
IEICE Trans. on Inf. and Syst.   Vol. E100-D(No.9) 2232-2236   Sep 2017   [Refereed]
A Unified Test and Fault-Tolerant Multicast Solution for Network-on-Chip Designs
Dong Xiang, Krishnendu Chakrabarty, and Hideo Fujiwara
IEEE International Test Conference 2016      Nov 2016   [Refereed]
Realization of SR-Equivalents Using Generalized Shift Registers for Secure Scan Design
Hideo Fujiwara and Katsuya Fujiwara
IEICE Trans. on Inf. and Syst.   Vol. E99-D(No. 8) 2182-2185   Aug 2016   [Refereed]
Jun Nishimaki, Toshinori Hosokawa and Hideo Fujiwara
21st IEEE European Test Symposium (ETS'16)      May 2016   [Refereed]
Hideo Fujiwara and Katsuya Fujiwara
IEICE Trans. on Inf. and Syst.   Vol. E99-D(No. 4)    Apr 2016   [Refereed]
Dong Xiang, Krishnendu Chakrabarty, and Hideo Fujiwara
IEEE Trans. on Computers      2016   [Refereed]
Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa and Hideo Fujiwara
IEEE the 24th Asian Test Symposium   37-42   Nov 2015   [Refereed]
A Scheduling Method for Hierarchical Testability Using Results of Test Environment Generation
Jun Nishimaki, Toshinori Hosokawa and Hideo Fujiwara
15th IEEE Workshop on RTL and High Level Testing (WRTLT'14)      Nov 2015   [Refereed]

Books etc

 
9 books
2008   
till 2008
Basic Logic and Mathematics of Switching Theory
Ohm-Sha   1980   
Fault Diagnosis of Digital Circuits
Kogakutosho   1983   
Logic Testing and Design for Testability
MIT Press   1985   
Introduction to Computer Design
Kogakutosho   1998   

Works

 
STARC (Semiconductor Technology Academic Research Center) "Research on High Level Synthesis of High Performance and High Testability VLSI Circuits"
1997 - 2000
STARC (Semiconductor Technology Academic Research Center) "Research and Development on V-Core Based Design for Testability Technology"
2000 - 2002
TAO (Telecommunications Advancement Organization of Japan) "Research on High-Speed and High-Reliable Satellite Communication Systems"
1996 - 1998
STARC (Semiconductor Technology Academic Research Center) "Research on Instruction-level Self-test and Design-for-testability for Processors"
2003 - 2005
RSTARC (Semiconductor Technology Academic Research Center) "Research on test time and yield loss reduction through false path indentification and its propagation from behavioral to structural representations"
2006 - 2008

Research Grants & Projects

 
Study on Design Automation of Computers
Study on Fault Tolerant Computers
Study on Hardware/Software Codesign

Patents

 
Mothod of design for testalility and method of test segeuence generation
6,292,915
Testable Integrated Cirauit,Integrated Ciram't Design-for-Testbility Method,and Compiter-Readable Medium Storing A Program for INplementing The Design-for-Testability Meitod
6334200B1
Integrated Circuits and its Design Method
09/699478