Misc.

Jan 30, 2013

Design and performance of pseudo-spin-MOSFETs using nano-CMOS devices

Technical report of IEICE. SDM
  • SHUTO Yusuke
  • ,
  • YAMAMOTO Shuu'ichirou
  • ,
  • SUKEGAWA Hiroaki
  • ,
  • Wen ZhenChao
  • ,
  • NAKANE Ryosho
  • ,
  • MITANI Seiji
  • ,
  • TANAKA Masaaki
  • ,
  • INOMATA Koichiro
  • ,
  • SUGAHARA Satoshi

Volume
112
Number
421
First page
43
Last page
46
Language
Japanese
Publishing type
Publisher
The Institute of Electronics, Information and Communication Engineers

The design and performance of pseudo-spin-MOSFETs (PS-MOSFETs) using nano-CMOS devices were computationally investigated The operations of a PS-MOSFET with current-induced magnetization switching were also expenmentally demonstrated by the hybrid integration of a vendor-made MOSFET and our-developed spin-transfer-torque magnetic tunnel junction The nonvolatile SRAM and delay flip-flop applications of PS-MOSFETs were also examined, and nonvolatile power-gating architecture using these circuits was developed.

Link information
CiNii Articles
http://ci.nii.ac.jp/naid/110009728061
CiNii Books
http://ci.nii.ac.jp/ncid/AN10013254
ID information
  • ISSN : 0913-5685
  • CiNii Articles ID : 110009728061
  • CiNii Books ID : AN10013254
  • identifiers.cinii_nr_id : 9000002762753

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