MISC

査読有り
2013年

Monolithic integration of pseudo-spin-MOSFETs using a custom CMOS chip fabricated through multi-project wafer service

2013 PROCEEDINGS OF THE EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC)
  • R. Nakane
  • ,
  • Y. Shuto
  • ,
  • H. Sukegawa
  • ,
  • Z. C. Wen
  • ,
  • S. Yamamoto
  • ,
  • S. Mitani
  • ,
  • M. Tanaka
  • ,
  • K. Inomata
  • ,
  • S. Sugahara

開始ページ
272
終了ページ
275
記述言語
英語
掲載種別
DOI
10.1109/ESSDERC.2013.6818871
出版者・発行元
IEEE

We demonstrated monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depended on the surface roughness of the passivation film. Nevertheless, after the chip surface was atomically flattened by SiO2 deposition and successive chemical-mechanical polish (CMP) process, the fabricated MTJs on the surface exhibited a sufficiently large TMR ratio (> 140 %) adaptable to the PS-MOSFET application. The implemented PS-MOSFETs showed clear modulation of the output current controlled by the magnetization configuration of the MTJs, and a maximum magnetocurrent ratio of 90 % was achieved. These magnetocurrent behaviors were quantitatively consistent with those predicted by HSPICE simulations. The developed integration technique using a MPW CMOS chip would also be applied to monolithic integration of CMOS devices/circuits and other various functional devices/materials, which would open the door for exploring CMOS-based new functional hybrid circuits.


リンク情報
DOI
https://doi.org/10.1109/ESSDERC.2013.6818871
Web of Science
https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:000342231600065&DestApp=WOS_CPL
URL
http://orcid.org/0000-0002-4034-7848

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