Mar 6, 2012
D-6-3 A Method for Size Reduction of Asynchronous Circuits using Maximum Delay Loop in Dependency Graphs
Proceedings of the IEICE General Conference
- ,
- ,
- Volume
- 2012
- Number
- 1
- First page
- 64
- Last page
- 64
- Language
- Japanese
- Publishing type
- Publisher
- The Institute of Electronics, Information and Communication Engineers
- Link information
-
- CiNii Articles
- http://ci.nii.ac.jp/naid/110009461237
- CiNii Books
- http://ci.nii.ac.jp/ncid/AN10471452
- ID information
-
- CiNii Articles ID : 110009461237
- CiNii Books ID : AN10471452