Apr 25, 1996
Pipelining Algorithm of Dependency Graphs for Asynchronous Processor Design
Technical report of IEICE. ICD
- ,
- ,
- Volume
- 96
- Number
- 20
- First page
- 9
- Last page
- 16
- Language
- Japanese
- Publishing type
- Publisher
- The Institute of Electronics, Information and Communication Engineers
Dependency graphs that represent specifications of systems such as processors can be easily mapped into asynchronous circuits. It, however, has not been known how to derive pipelined dependency graphs systematically. In this paper, we propose an algorithm that can transform given dependency graphs representing repeated execution of operations into pipelined graphs by (1) searching for all pairs of operations that can be pipelined and (2) applying a graph transformation to paths between operations of each pair.
- Link information
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- CiNii Articles
- http://ci.nii.ac.jp/naid/110003316788
- CiNii Books
- http://ci.nii.ac.jp/ncid/AN10013276
- ID information
-
- CiNii Articles ID : 110003316788
- CiNii Books ID : AN10013276