論文

査読有り
2017年12月

A Layout-Oriented Routing Method for Low-Latency HPC Networks

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
  • Ryuta Kawano
  • ,
  • Hiroshi Nakahara
  • ,
  • Ikki Fujiwara
  • ,
  • Hiroki Matsutani
  • ,
  • Michihiro Koibuchi
  • ,
  • Hideharu Amano

E100D
12
開始ページ
2796
終了ページ
2807
記述言語
英語
掲載種別
研究論文(学術雑誌)
DOI
10.1587/transinf.2017PAP0019
出版者・発行元
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

End-to-end network latency has become an important issue for parallel application on large-scale high performance computing (HPC) systems. It has been reported that randomly-connected inter-switch networks can lower the end-to-end network latency. This latency reduction is established in exchange for a large amount of routing information. That is, minimal routing on irregular networks is achieved by using routing tables for all destinations in the networks. In this work, a novel distributed routing method called LOREN (Layout-Oriented Routing with Entries for Neighbors) to achieve low-latency with a small routing table is proposed for irregular networks whose link length is limited. The routing tables contain both physically and topologically nearby neighbor nodes to ensure livelock-freedom and a small number of hops between nodes. Experimental results show that LOREN reduces the average latencies by 5.8% and improves the network throughput by up to 62% compared with a conventional compact routing method. Moreover, the number of required routing table entries is reduced by up to 91%, which improves scalability and flexibility for implementation.

Web of Science ® 被引用回数 : 1

リンク情報
DOI
https://doi.org/10.1587/transinf.2017PAP0019
Web of Science
https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:000417990300006&DestApp=WOS_CPL