Papers

Peer-reviewed
Dec, 2017

A Layout-Oriented Routing Method for Low-Latency HPC Networks

IEICE Transactions on Information and Systems
  • Ryuta Kawano
  • ,
  • Hiroshi Nakahara
  • ,
  • Ikki Fujiwara
  • ,
  • Hiroki Matsutani
  • ,
  • Michihiro Koibuchi
  • ,
  • Hideharu Amano

Volume
E100-D
Number
12
First page
2796
Last page
2807
Language
English
Publishing type
Research paper (scientific journal)
DOI
10.1587/transinf.2017PAP0019
Publisher
The Institute of Electronics, Information and Communication Engineers

<p>End-to-end network latency has become an important issue for parallel application on large-scale high performance computing (HPC) systems. It has been reported that randomly-connected inter-switch networks can lower the end-to-end network latency. This latency reduction is established in exchange for a large amount of routing information. That is, minimal routing on irregular networks is achieved by using routing tables for all destinations in the networks. In this work, a novel distributed routing method called LOREN (Layout-Oriented Routing with Entries for Neighbors) to achieve low-latency with a small routing table is proposed for irregular networks whose link length is limited. The routing tables contain both physically and topologically nearby neighbor nodes to ensure livelock-freedom and a small number of hops between nodes. Experimental results show that LOREN reduces the average latencies by 5.8% and improves the network throughput by up to 62% compared with a conventional compact routing method. Moreover, the number of required routing table entries is reduced by up to 91%, which improves scalability and flexibility for implementation.</p>

Link information
DOI
https://doi.org/10.1587/transinf.2017PAP0019
CiNii Articles
http://ci.nii.ac.jp/naid/130006236565
ID information
  • DOI : 10.1587/transinf.2017PAP0019
  • CiNii Articles ID : 130006236565

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