2010年
Enabling false path identification from RTL for reducing design and test futileness
Proceedings - 5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010
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- 開始ページ
- 20
- 終了ページ
- 25
- 記述言語
- 英語
- 掲載種別
- 研究論文(国際会議プロシーディングス)
- DOI
- 10.1109/DELTA.2010.23
- 出版者・発行元
- IEEE Computer Society
Information on false paths is useful for design and test. Since identification of false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and at gate level can be established. Until now, the correspondence has been established only by some restricted logic synthesis. In this paper, we propose a method for mapping RTL false paths to their corresponding gate level paths without such a specific logic synthesis. © 2010 IEEE.
- リンク情報
- ID情報
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- DOI : 10.1109/DELTA.2010.23
- DBLP ID : conf/delta/IwataOF10
- SCOPUS ID : 77952329310