論文

査読有り
2014年

A sophisticated routing algorithm in 3D NoC with fixed TSVs for low energy and latency

IPSJ Transactions on System LSI Design Methodology
  • Xin Jiang
  • ,
  • Lian Zeng
  • ,
  • Takahiro Watanabe

7
開始ページ
101
終了ページ
109
記述言語
英語
掲載種別
研究論文(学術雑誌)
DOI
10.2197/ipsjtsldm.7.101
出版者・発行元
Information Processing Society of Japan

With rapid progress in Integrated Circuit technologies, Three-Dimensional Network-on-Chips (3DNoCs) have become a promising solution for achieving low latency and low power. Under the constraint of the TSV number used in 3DNoCs, designing a proper routing algorithm with fewer TSVs is a critical problem for network performance improvement. In this work, we design a novel fully adaptive routing algorithm in 3D NoC. The algorithm consists of two parts: one is a vertical node assignment in inter-layer routing, which is a TSV selection scheme in a limited quantity of TSVs in the NoC architecture, and the other is a 2D fully adaptive routing algorithm in intra-layer routing, which combines the optimization of routing distance, network traffic condition and diversity of the path selection. Simulation results show that our proposed routing algorithm can achieve lower latency and energy consumption compared with other traditional routing algorithms.

リンク情報
DOI
https://doi.org/10.2197/ipsjtsldm.7.101
ID情報
  • DOI : 10.2197/ipsjtsldm.7.101
  • ISSN : 1882-6687
  • SCOPUS ID : 84986891177

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