Jiro Ida

Evaluation of Multi-Finger PN-Body Tied SOI-FET-Origin and Suppression of Stepped I_d–V_g Characteristics-

Takayuki Mori, Kengo Nakata, Jiro Ida

2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Apr 18, 2022

Neuron Function with Single Device by using "PN-Body Tied SOI-FET"-Mimicking Leaky Integrate and Fire Characteristics-

Toru Sasaki, Takayuki Mori, Jiro Ida

2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Mar 6, 2022

RF Evaluation of Steep Subthreshold Slope “PN-Body Tied SOI-FET”

Mitsuhiro Yuizono, Jiro Ida, Takayuki Mori, Koichiro Ishibashi

2021 IEEE International Meeting for Future Electron Devices, Kansai (IMFEDK), Nov 17, 2021

Developing Ultralow Trun-on Voltage Diode by Steep Slope "PN-Body Tied SOI-FET"

Masayuki Ono, Jiro Ida, Takayuki Mori, Koichiro Ishibashi

2021 IEEE International Meeting for Future Electron Devices, Kansai (IMFEDK), Nov 17, 2021

Investigation of capacitor-less integrate and fire neuron by using dual-gate a PN-body tied silicon on insulator field-effect transistor

Takayuki Mori, Jiro Ida

Japanese Journal of Applied Physics, 60(SB) SBBA04-SBBA04, May 1, 2021 Peer-reviewed

Transfer Characteristics of CMOS Inverter using "Steep SS PN-Body Tied SOI-FET"

Shota Ishiguro, Jiro Ida, Takayuki Mori, Koichiro Ishibashi

2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Apr 19, 2021

Analysis of Drain Current Enhancement in "PN-Body Tied SOI-FET" -Bulk vs Surface Conduction Mode and Low Vds Saturation Effect-

Hiroki Itoh, Jiro Ida, Takayuki Mori, Koichiro Ishibashi

2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Apr 19, 2021

Neuron Circuit Using Dual Gate PN Body-Tied SOI-FET

Mori Takayuki, Ida Jiro

JSAP Annual Meetings Extended Abstracts, 2021.1 2346-2346, Feb 26, 2021

Transient Characteristics on Super-Steep Subthreshold Slope “PN-Body Tied SOI-FET” — Simulation and Pulse Measurement —

Takayuki MORI, Jiro IDA, Hiroki ENDO

IEICE Transactions on Electronics, E103.C(10) 533-542, Oct 1, 2020 Peer-reviewed

Analysis of Saturation Effect at Low Vds appearing in PN-Body Tied SOI-FET

Ito Hiroki, Ida Jiro, Mori Takayuki

JSAP Annual Meetings Extended Abstracts, 2020.2 1839-1839, Aug 26, 2020

Analysis of Steep SS Mechanism on PN-Body Tied SOI-FET with 65 nm Thin Box FD-SOI

Takayuki Mori, Jiro Ida, Keita Daimatsu

2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Aug, 2020 Peer-reviewed

PN-Body Tied SOI-FETでの電流増幅効果の解析-Bulk vs Surface伝導の比較-

井田次郎

第67回応用物理学会春期予稿集, 12p-A305-4, 2020年3月12日著者：伊藤広喜，井田次郎，森貴之, Mar, 2020

PN Body-Tied SOI-FETのニューロモルフィック応用

井田次郎

第67回応用物理学会春期予稿集, 14p-A301-7 , 2020年3月14 著者：森貴之，井田次郎, 遠藤大貴, 佐々木貫, Mar, 2020

Analysis of Drain Current Enhancement Effect on PN-Body Tied SOI-FET -Comparison of Bulk vs Surface Conduction-

Ito Hiroki, Ida Jiro, Mori Takayuki

JSAP Annual Meetings Extended Abstracts, 2020.1 2714-2714, Feb 28, 2020

Super steep SS "PN-Body tied SOI-FET" with 65 nm thin Box FD-SOI

Keita Daimatsu, Jiro Ida, Takuya Yamada, Takayuki Mori, Koichiro Ishibashi

2019 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) PROCEEDINGS, p117-118, 2019, November 13-15, 2019 Sofitel Chengdu Taihe, Chengdu, Sichuan, China, Nov, 2019 Peer-reviewed

Effect of Vsub and Positive Charge in Buried Oxide on Super Steep SS "PN Body-Tied SOI-FET" and Proposal of CMOS without Vsub Bias

IDA Jiro

PROCEEDINGS of IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S), session 5.06, pp1-3, 2019 Authors:Wataru Yabuki, Jiro Ida, Takayuki Mori, Koichiro Ishibashi and Yasuo Arai, Oct, 2019 Peer-reviewed

RF Characteristics of Rectifier Devices for Ambient RF Energy Harvesting (Invited)

IDA Jiro

2019 International Symposium on Electronics and Smart Devices (ISESD), Oct. 2019, Bali, Indonesia Authors:Koichiro Ishibashi, Jiro Ida, Linh-Thuy Nguyen, Ryo Ishikawa, Yasuo Satoh, and Duy-Manh Luong,, Oct, 2019 Peer-reviewed

Data of "PN-Body-Tied SOI-FET" manufactured using 65 nm thin BOX FDSOI

Daimatsu Keita, Ida Jiro, Yamada Takuya, Mori Takayuki

JSAP Annual Meetings Extended Abstracts, 2019.2 3114-3114, Sep 4, 2019

リーク電流低減に向けた新構造PN-Body-Tied SOI-FETの提案

井田次郎

第80回応用物理学会秋期予稿集,18p-B11-4, 2019年9月18 著者：森貴之，井田次郎, 遠藤大貴, Sep, 2019

65 nm thin BOX FDSOIでの急峻SS“PN-Body-Tied SOI-FET”特性確認

井田次郎

第80回応用物理学会秋期予稿集, 18p-B11-3, 2019年9月18 著者：大松啓太，井田次郎, 山田拓弥, 森貴之, Sep, 2019

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