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COUNTER186879FROM 2012/5/16

HDL(hardware description language) Diary

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2013/04/11

SystemVerilogの新機能

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16.1.1 平行プロセスjoin_anyとjoin_noneの追加

module fork_test2;
  task  my_task;
                $display("Hi  %d ",$time);               
  endtask 

initial begin
    fork//:Fork_Join
       #5  my_task;//process1
       #10 my_task;//process2
    join
    $display("Join Any Time=%d",$time); 
end

initial begin
    fork//:Fork_Any
       #5  my_task;//process1
       #10 my_task;//process2
    join_any//Error (10170): Verilog HDL syntax error at fork_test2.sv(24) near text "join_any";  expecting ";"
    $display("Join Any Time=%d",$time); 
end//Error (10170): Verilog HDL syntax error at fork_test2.sv(26) near text "end";  expecting ";"

initial begin
    fork//:Fork_None
       #5  my_task;//process1
       #10 my_task;//process2
    join_none//Error (10170): Verilog HDL syntax error at fork_test2.sv(34) near text "join_none";  expecting ";"
    $display("Join None Time=%d",$time); 
end//Error (10170): Verilog HDL syntax error at fork_test2.sv(36) near text "end";  expecting ";"
endmodule 


2) 8ビットASCII文字単位で、変数に代入することが出来ます。

module string_literal_test;//Error (12061): Can't synthesize current design -- Top partition does not contain any logic

byte c = "A"; // assigns to c "A"
integer c1 = "A";
 
bit [5:0][7:0] d="ABCD";
logic [2:0][7:0] e="ABCDE";
  
         initial begin
$display("c=%s",c);
$display("c=%s",c1);
$display("d=%s %x",d,d);
$display("e=%s %x",e,e);
end

endmodule

Error (10170): Verilog HDL Syntax Error at <filename> near text "int"; expecting an identifier ("int" is a reserved keyword)

Quartus II によるSystemVerilog のサポート

Settings -> Analysis & Synthesis Settings -> Verilog HDL Input -> Verilog version. By default it's Verilog-2001. Set to SystemVerilog-2005 to enable use of sv keywords and features.

上記の指示に従って、分析合成をSystemVerilogに設定しても、まだ誤り(ERROR)だと言われる。言語仕様というより処理系の実装状況によるかも。

--top.sv
//synthesis VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
module top;
        reg r;
        task t1;
                r=0;//moduleから呼ばれたらActive Region/ programから呼ばれたらReActive Region
                #2;// moduleから呼ばれたらActive Region/ programから呼ばれたらReActive Region
                r<=1;//moduleから呼ばれたらNBA Region/ programから呼ばれたらReNBA Region
        endtask
        function f1;
                r=!r;//moduleから呼ばれたらActive Region/ programから呼ばれたらReActive Region
        endfunction
 
        initial begin
                t1;
                f1;
        end
        prg test_bench();
endmodule

program prg;//Error (10170): Verilog HDL syntax error at top.sv(20) near text "program";  expecting a description
        initial begin
                #10
                top.t1;
                top.f1;
        end
endprogram

--top.qsf
set_global_assignment -name FAMILY "Cyclone IV GX"
set_global_assignment -name DEVICE auto
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:00:20  APRIL 11, 2013"
set_global_assignment -name LAST_QUARTUS_VERSION 12.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY ON -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name SYSTEMVERILOG_FILE top.sv
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SDC_FILE top.sdc
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Thread: SystemVerilog Extensions Error

 Error (12061): Can't synthesize current design -- Top partition does not contain any

Thread: Top Design Logic - Where?

I added port variable and output line.

module example1(data_wire);// Error (12061): Can't synthesize current design -- Top partition does not contain any logic
output data_wire; //Added
  logic data_wire; 
  logic data_reg;  
  logic sel;
  logic datain;
  logic clk;

  always @(*)
    begin
      case (sel)
 1'b0: data_wire <= datain;
 1'b1: data_wire <= ~datain;
endcase // case(sel)
    end

  always @(posedge clk)
    data_reg <= datain;
endmodule

--Model Sim for Altera starter
# -- Compiling module example1
# Top level modules:
# example1
vsim -do example1_run_msim_gate_systemverilog.do -l msim_transcript -gui work.example1
# vsim -do example1_run_msim_gate_systemverilog.do -l msim_transcript -gui work.example1 
# Loading sv_std.std
# Loading work.example1
# ** Error: (vsim-3033) example1.svo(64): Instantiation of 'cycloneiv_io_obuf' failed. The design unit was not found.
#         Region: /example1
#         Searched libraries:
#             C:/altera/forum/example1/simulation/modelsim/gate_work
# Error loading design

Thread: How to fix "the design unit was not found" in modelsim simulation?

Thread: How to add path to Modelsim to correct "the design unit was not found"?
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2013/04/11

SystemVerilog事始め

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02. Hello World!!
module test;//Warning (12158): Entity "test" contains only dangling pins
    initial begin
        $display("Hello World!!");//Error (12061): Can't synthesize current design -- Top partition does not contain any logic

    end
endmodule
//Error: Quartus II 64-Bit Analysis & Elaboration was unsuccessful. 1 error, 1 warning
//Error: Peak virtual memory: 482 megabytes
//Error: Processing ended: Thu Apr 11 11:39:06 2013
//Error: Elapsed time: 00:00:01
//Error: Total CPU time (on all processors): 00:00:01
//Error (293001): Quartus II Flow was unsuccessful. 3 errors, 1 warning

03. 配列の基本 02. 動的配列

module test;
  initial begin
    int array[];//Error (10170): Verilog HDL syntax error at test.sv(3) near text "]";  expecting an operand
    int elements;
    elements = 5;
    array = new[elements];//Error (10170): Verilog HDL syntax error at test.sv(6) near text "new";  expecting an operand
    for(int i=0; i<elements; i++)begin
      array[i]=i;
    end
    for(int i=0; i<elements; i++)begin
      $display("array[%0d] = %0d", i, array[i]);
    end
  end
endmodule

module test;
  task test_task (int a, output int b);
    #10 b = a*10;
  endtask

  initial begin
    int c;
    test_task(10,c);
    $display("[%0d] c=%0d",$time,c);//Error (10174): Verilog HDL Unsupported Feature error at test.sv(9): system function "$time" is not supported for synthesis

  end
endmodule

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2013/04/10

SystemVerilog設計スタートアップ

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の7,8,9章のコードをCQ出版のWEBに掲載している。

AlteraのQuartus II Web Edition SoftwareはSystemVerilogに対応しているとのこと。
早速無償版を落として導入し、動作確認をしている。

7章のコードを4つともファイルとして読み込んでコンパイルする。

ERROR 1 
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top
Info (20029): Only one processor detected - disabling parallel compilation
Info (12021): Found 2 design units, including 2 entities, in source file top.sv
Info (12023): Found entity 1: top
Info (12023): Found entity 2: top_pm
Info (12021): Found 1 design units, including 1 entities, in source file proc.sv
Info (12023): Found entity 1: proc
Info (12021): Found 1 design units, including 1 entities, in source file memory.sv
Info (12023): Found entity 1: memory
Info (12021): Found 2 design units, including 2 entities, in source file cache.sv
Info (12023): Found entity 1: cache
Info (12023): Found entity 2: cache_set
Warning (10227): Verilog HDL Port Declaration warning at proc.sv(24): data type declaration for "addr" declares packed dimensions but the port declaration declaration does not
Info (10499): HDL info at proc.sv(14): see declaration for object "addr"
Warning (10227): Verilog HDL Port Declaration warning at proc.sv(25): data type declaration for "data" declares packed dimensions but the port declaration declaration does not
Info (10499): HDL info at proc.sv(15): see declaration for object "data"
Warning (10227): Verilog HDL Port Declaration warning at cache.sv(26): data type declaration for "paddr" declares packed dimensions but the port declaration declaration does not
Info (10499): HDL info at cache.sv(14): see declaration for object "paddr"
Warning (10227): Verilog HDL Port Declaration warning at cache.sv(28): data type declaration for "pdata" declares packed dimensions but the port declaration declaration does not
Info (10499): HDL info at cache.sv(16): see declaration for object "pdata"
Warning (10227): Verilog HDL Port Declaration warning at cache.sv(27): data type declaration for "maddr" declares packed dimensions but the port declaration declaration does not
Info (10499): HDL info at cache.sv(15): see declaration for object "maddr"
Warning (10227): Verilog HDL Port Declaration warning at cache.sv(28): data type declaration for "mdata" declares packed dimensions but the port declaration declaration does not
Info (10499): HDL info at cache.sv(16): see declaration for object "mdata"
Warning (10227): Verilog HDL Port Declaration warning at cache.sv(180): data type declaration for "addr" declares packed dimensions but the port declaration declaration does not
Info (10499): HDL info at cache.sv(176): see declaration for object "addr"
Warning (10227): Verilog HDL Port Declaration warning at cache.sv(184): data type declaration for "data" declares packed dimensions but the port declaration declaration does not
Info (10499): HDL info at cache.sv(177): see declaration for object "data"
Warning (10227): Verilog HDL Port Declaration warning at memory.sv(28): data type declaration for "addr" declares packed dimensions but the port declaration declaration does not
Info (10499): HDL info at memory.sv(13): see declaration for object "addr"
Warning (10227): Verilog HDL Port Declaration warning at memory.sv(29): data type declaration for "data" declares packed dimensions but the port declaration declaration does not
Info (10499): HDL info at memory.sv(15): see declaration for object "data"
Info (12127): Elaborating entity "top" for the top level hierarchy
Warning (10755): Verilog HDL warning at top.sv(30): assignments to clk create a combinational loop
Info (12128): Elaborating entity "proc" for hierarchy "proc:p"
Warning (10230): Verilog HDL assignment warning at proc.sv(61): truncated value with size 32 to match size of target (16)
Error (10174): Verilog HDL Unsupported Feature error at proc.sv(67): system function "$time" is not supported for synthesis
Info (10648): Verilog HDL Display System Task info at proc.sv(67): %t: Starting Read/Write test
Info (10648): Verilog HDL Display System Task info at proc.sv(89): Read/Write test done
Warning (10175): Verilog HDL warning at proc.sv(90): ignoring unsupported system task
Error (12152): Can't elaborate user hierarchy "proc:p"
Info (144001): Generated suppressed messages file C:/altera/sample_data/7sho/example/output_files/top.map.smsg
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 2 errors, 13 warnings
Error: Peak virtual memory: 477 megabytes
Error: Processing ended: Wed Apr 10 14:13:43 2013
Error: Elapsed time: 00:00:06
Error: Total CPU time (on all processors): 00:00:01
Error (293001): Quartus II Full Compilation was unsuccessful. 4 errors, 13 warnings

1つのエラーが、合成では$timeに対応していないとのこと。
この状態は Compilation である。
RTL Simulation
Gate Level Simulation
を試してみる。

Error2 
You did not specify an EDA simulation tool.

Simulatorを導入していなかった。
Simulator(Model Simだけ導入したら対応する版が違い連携させかたがわからず)
Model Simと同時にQuartus IIを別の機材で導入して
RTL Simulation
Gate Level Simulation
を試してみる。

Error2以降の時間はほぼ1日。

Errorの種類、数はかわらず。

$time Quartusで検索


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2013/04/10

SystemVerilog 対応始めました

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2001年版(v3と表記)の大きな違いは、
SystemVerilogに対応したことと、
検証系を補強したこと
clockまわりを改訂したこと
の3つを確認している。

AlteraのQuartus II Web Edition SoftwareはSystemVerilogに対応しているとのこと。
早速無償版を落として導入し、SystemVerilogの動作確認を始めました。

FPGAの2大製造元の道具に対応することにより、VerilogまわりのFPGAの動向を把握することができるのも大切なことだからです。

QuartusII Web Edition Software導入にあたっては、途中Microsoft社のVisual C++ 2008の更新の作業があった。

2.12. データタイプの拡張(SystemVerilog 編)
2.12.1. reg とwire をlogic におきかえる

Verilog HDLでは,記憶素子を含むregと配線の機能のwireを区別して使用していた。
厳密にregは記憶素子になるかというと、必ずしもそうでないため紛らわしい面があった。

SystemVerilogではlogicで統一的に書けるとのこと。

2.12.2. パック型配列を活用する
VerilogHDLでの配列はUnpackであるのに対して、SystemVerilogではpackedが使える。

2.12.3. 構造体と共用体を活用する

2.12.4. ステートマシンの記述に列挙型を使う

2.13. 新しいalways 文(SystemVerilog 編)
2.13.1. always_comb による組み合わせ回路の記述
2.13.2. always_ff による順序回路の記述
2.13.3. always_latch によるラッチ回路の記述

2.14. if 文とcase 文の拡張(SystemVerilog 編)
2.14.1. priority とunique の使用方法に注意する

2.15. モジュール、ファンクション宣言と接続(Verilog-2001, SystemVerilog編)
2.15.1. ANSI C スタイルのモジュール宣言を使用する

参考資料
SystemVerilog の魅力 1 (基礎編)
SystemVerilog Tutorial  
SystemVerilog設計スタートアップ
13:08 | Impressed! | Voted(0) | Comment(0)
2013/04/09

例3-8 上位階層からのパラメータの書き換えの記述例

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の例をコンパイルできる状態にする。内容の検討は、コンパイルできる状態が著者の意図を外していないかを確認しながら進む(予定)。

3.2. 機能ライブラリの使用
3.2.3. コンポーネント接続にはポート名接続を使用する
例3-8 上位階層からのパラメータの書き換えの記述例   

// (c)STARC RTL 設計スタイルガイドVerilog HDL編 第二版(v2), 2001年版(v3)
SEL4TO1 #(32) MSEL1(.DIN0(DIN), .DIN1(AIN), .DIN2(BIN), .DIN3(CIN), .SEL(SEL1), .Y(Y1));
SEL4TO1 #(16,8) MSEL2(.DIN0(LIN), .DIN1(RIN), .DIN2(SIN), .DIN3(TIN), .SEL(SEL2), .Y(Y2));

<この稿は書きかけです。随時追記します。>
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改善の本棚(booklog)
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2013/04/09

例3-7 下位ブロック接続の記述例

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の例をコンパイルできる状態にする。内容の検討は、コンパイルできる状態が著者の意図を外していないかを確認しながら進む(予定)。

3.2. 機能ライブラリの使用
3.2.3. コンポーネント接続にはポート名接続を使用する
例3-7 下位ブロック接続の記述例   
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    09:58:25 04/09/2013 
// Design Name: 
// Module Name:    starc_3_7 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
// (c)STARC RTL 設計スタイルガイドVerilog HDL編 第二版(v2), 2001年版(v3)
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module starc_3_7(CLK1, RESET3, CI1,DATA1, CI2,CI3
    );
input CLK1, RESET3,CI1;
output DATA1, CI2,CI3;
//ポート名接続
CNT8 CNT8(.CLK(CLK1), .RST(RESET3), .CARRYIN(CI1), .CARRYOUT(DATA1), .DOUT(CI2));
//ポート順接続
CNT8 CNT9(CLK1, RESET3, CI1, DATA1, CI3);// この接続は禁止(同じ名前が使えないのでインスタンス名を変更している)
endmodule

module CNT8(CLK, RST, CARRYIN, CARRYOUT, DOUT);
input CLK,RST,CARRYIN;
output CARRYOUT, DOUT;
assign DOUT = CLK & RST;
assign CARRYOUT = CARRYIN;
endmodule

<この稿は書きかけです。随時追記します。>
Twitter:@kaizen_nagoya
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09:52 | Impressed! | Voted(0) | Comment(0)
2013/04/09

v3例2-63 reg, wireによる信号宣言とlogicによる信号宣言

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の例をコンパイルできる状態にする。内容の検討は、コンパイルできる状態が著者の意図を外していないかを確認しながら進む(予定)。

v3 2.12. データタイプの拡張(SystemVerilog 編)
v3 2.12.1. reg とwire をlogic におきかえる
v3例2-63 reg, wireによる信号宣言とlogicによる信号宣言
// (c)STARC RTL 設計スタイルガイドVerilog HDL編 2001年版(v3)
//Verilog HDL
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    09:27:19 04/09/2013 
// Design Name: 
// Module Name:    starc_o_2_63 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
// (c)STARC RTL 設計スタイルガイドVerilog HDL編 2001年版(v3)
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module starc_o_2_63(MODE, AIN,BIN,ACCOUT,CMPOUT
    );
input MODE, AIN,BIN;
output ACCOUT,CMPOUT;
wire MODE;
wire [3:0] AIN, BIN;
reg [3:0] ACCOUT;
wire CMPOUT;
always @(MODE or AIN or BIN) begin
if (MODE == 1'b1)
ACCOUT = AIN + BIN;
else
ACCOUT = AIN - BIN;
end
assign CMPOUT = (AIN < BIN);

endmodule

// (c)STARC RTL 設計スタイルガイドVerilog HDL編 2001年版(v3)
//System Verilog
module starc_O_2_63sys(MODE, AIN,BIN,ACCOUT,CMPOUT
    );
input MODE;
input [3:0]AIN;
input [3:0] BIN;
output ACCOUT, CMPOUT;
logic MODE; // ERROR:HDLCompilers:26 - "starc_O263sys.v" line 25 unexpected token: 'MODE'
logic [3:0] AIN, BIN;//ERROR:HDLCompilers:26 - "starc_O263sys.v" line 28 unexpected token: '['
logic [3:0] ACCOUT;
logic CMPOUT;
always_comb begin
if (MODE == 1'b1)
ACCOUT = AIN + BIN;
else
ACCOUT = AIN - BIN;
end
assign CMPOUT = (AIN < BIN);

endmodule
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue Apr 09 17:44:39 2013
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off starc_sample -c starc_sample
Info (20029): Only one processor detected - disabling parallel compilation
Info (12021): Found 1 design units, including 1 entities, in source file work/starc_sample.sv
Info (12023): Found entity 1: starc_O_2_63sys
Info (12021): Found 1 design units, including 1 entities, in source file work/systemverilog1.sv
Info (12023): Found entity 1: starc_sample
Warning (10227): Verilog HDL Port Declaration warning at starc_sample.sv(10): data type declaration for "ACCOUT" declares packed dimensions but the port declaration declaration does not
Info (10499): HDL info at starc_sample.sv(7): see declaration for object "ACCOUT"
Warning (10227): Verilog HDL Port Declaration warning at SystemVerilog1.sv(10): data type declaration for "ACCOUT" declares packed dimensions but the port declaration declaration does not
Info (10499): HDL info at SystemVerilog1.sv(7): see declaration for object "ACCOUT"
Info (12127): Elaborating entity "starc_sample" for the top level hierarchy
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 26 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 9 input pins
Info (21059): Implemented 5 output pins
Info (21061): Implemented 12 logic cells
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 479 megabytes
Info: Processing ended: Tue Apr 09 17:44:44 2013
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:02
Info: *******************************************************************
Info: Running Quartus II 64-Bit Fitter
Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue Apr 09 17:44:49 2013
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off starc_sample -c starc_sample
Info (20029): Only one processor detected - disabling parallel compilation
Info (119006): Selected device EP4CGX15BN11C8 for design "starc_sample"
Info (21077): Core supply voltage is 1.2V
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info (169124): Fitter converted 5 user pins into dedicated programming pins
Info (169125): Pin ~ALTERA_NCEO~ is reserved at location A28
Info (169125): Pin ~ALTERA_DATA0~ is reserved at location A74
Info (169125): Pin ~ALTERA_ASDO~ is reserved at location B63
Info (169125): Pin ~ALTERA_NCSO~ is reserved at location A75
Info (169125): Pin ~ALTERA_DCLK~ is reserved at location B64
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Critical Warning (169085): No exact pin location assignment(s) for 14 pins of 14 total pins
Info (169086): Pin ACCOUT[0] not assigned to an exact location on the device
Info (169086): Pin ACCOUT[1] not assigned to an exact location on the device
Info (169086): Pin ACCOUT[2] not assigned to an exact location on the device
Info (169086): Pin ACCOUT[3] not assigned to an exact location on the device
Info (169086): Pin CMPOUT not assigned to an exact location on the device
Info (169086): Pin MODE not assigned to an exact location on the device
Info (169086): Pin BIN[0] not assigned to an exact location on the device
Info (169086): Pin AIN[0] not assigned to an exact location on the device
Info (169086): Pin BIN[1] not assigned to an exact location on the device
Info (169086): Pin AIN[1] not assigned to an exact location on the device
Info (169086): Pin BIN[2] not assigned to an exact location on the device
Info (169086): Pin AIN[2] not assigned to an exact location on the device
Info (169086): Pin BIN[3] not assigned to an exact location on the device
Info (169086): Pin AIN[3] not assigned to an exact location on the device
Critical Warning (332012): Synopsys Design Constraints File file not found: 'starc_sample.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained base clocks found in the design
Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
Info (176233): Starting register packing
Info (176235): Finished register packing
Extra Info (176219): No registers were packed into other blocks
Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info (176211): Number of I/O pins in group: 14 (unused VREF, 2.5V VCCIO, 9 input, 5 output, 0 bidirectional)
Info (176212): I/O standards used: 2.5 V.
Info (176215): I/O bank details before I/O pin placement
Info (176214): Statistics of I/O banks
Info (176213): I/O bank number QL0 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  0 pins available
Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  7 pins available
Info (176213): I/O bank number 3A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available
Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available
Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available
Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available
Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  14 pins available
Info (176213): I/O bank number 8A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  2 pins available
Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  5 pins available
Info (176213): I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  0 pins available
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:03
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X22_Y0 to location X33_Y9
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
Info (170201): Optimizations that may affect the design's routability were skipped
Info (170200): Optimizations that may affect the design's timing were skipped
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
Info (144001): Generated suppressed messages file C:/altera/output_files/starc_sample.fit.smsg
Info: Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 717 megabytes
Info: Processing ended: Tue Apr 09 17:45:06 2013
Info: Elapsed time: 00:00:17
Info: Total CPU time (on all processors): 00:00:06
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue Apr 09 17:45:20 2013
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off starc_sample -c starc_sample
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 459 megabytes
Info: Processing ended: Tue Apr 09 17:45:22 2013
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01
Info (293026): Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue Apr 09 17:45:23 2013
Info: Command: quartus_sta starc_sample -c starc_sample
Info: qsta_default_script.tcl version: #1
Info (20029): Only one processor detected - disabling parallel compilation
Info (21077): Core supply voltage is 1.2V
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'starc_sample.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info (332159): No clocks to report
Info: Analyzing Slow 1200mV 85C Model
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Fast 1200mV 0C Model
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 456 megabytes
Info: Processing ended: Tue Apr 09 17:45:26 2013
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:02
Info (293000): Quartus II Full Compilation was successful. 0 errors, 11 warnings


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2013/04/09

v3 例2-65 配列の部分選択の記述

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の例をコンパイルできる状態にする。内容の検討は、コンパイルできる状態が著者の意図を外していないかを確認しながら進む(予定)。

v3 2.12. データタイプの拡張(SystemVerilog編)
v3 2.12.2. パック型配列を活用する
v3例2-65 配列の部分選択の記述
// (c)STARC RTL 設計スタイルガイドVerilog HDL編 2001年版(v3)
wire CLK,RST_X,WRITE;
wire [1:0] ADDR;
wire [7:0] AIN;
reg [7:0] MEM1 [0:3]; // unpacked array
integer i;
always @(posedge CLK or negedge RST_X) begin
if (!RST_X)
for (i=0; i<4; i=i+1) begin
MEM1[i] <= 8'b0;
end
else if (WRITE)
MEM1[ADDR] <= AIN;
end
アンパック型配列(Verillog HDL記述)
パック型配列(SystemVerilog記述)
// (c)STARC RTL 設計スタイルガイドVerilog HDL編 2001年版(v3)
logic CLK,RST_X,WRITE;
logic [1:0] ADDR;
logic [7:0] BIN;
logic [0:3][7:0] MEM2; // packed array
always_ff @(posedge CLK or negedge RST_X) begin
if (!RST_X)
MEM2 <= 32'b0;
else if (WRITE)
MEM2[ADDR] <= BIN;
end

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