2018年6月10日
Impact of mutual inductance on timing in nano-scale SoC
IEICE Electronics Express
- ,
- ,
- ,
- 巻
- 15
- 号
- 11
- 開始ページ
- 20180376
- 終了ページ
- 20180376
- 記述言語
- 英語
- 掲載種別
- 研究論文(学術雑誌)
- DOI
- 10.1587/elex.15.20180376
- 出版者・発行元
- Institute of Electronics Information Communication Engineers
This paper investigates the impact of mutual inductance (M) on interconnect signal delay estimation according to resistance (R), inductance (L), and capacitance (C) in nano-scale system on a chip (SoC), suggesting a method to predict and suppress the impact. The proposed methodology first calculates the difference in delay between RLC and RLMC wire models for a set of parameter variations, then builds response surface functions (RSF) using physical parameters including wire width and spacing. The proposed method contributes to the following actions. 1) Describe design rules to avoid mutual inductance effects. 2) Select wires which require RLMC models for delay estimation. 3) Correct the estimated delay when using an RLC model. As an example, situations to limit the mutual inductance effect is shown as to a 14 nm technology node.
- リンク情報
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- DOI
- https://doi.org/10.1587/elex.15.20180376
- DBLP
- https://dblp.uni-trier.de/rec/journals/ieiceee/SakataHIK18
- Web of Science
- https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:000434975600011&DestApp=WOS_CPL
- URL
- https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85049137258&origin=inward
- ID情報
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- DOI : 10.1587/elex.15.20180376
- ISSN : 1349-2543
- DBLP ID : journals/ieiceee/SakataHIK18
- ORCIDのPut Code : 48939543
- SCOPUS ID : 85049137258
- Web of Science ID : WOS:000434975600011