2008年
EMC Macro-modeling of CMOS Inverter Using LECCS-I/O Model with Additional Current Source
2008 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, VOLS 1-3
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- 開始ページ
- 554
- 終了ページ
- +
- 記述言語
- 英語
- 掲載種別
- 出版者・発行元
- IEEE
The authors investigated an EMC macro-model of the CMOS logic inverter gate, named LECCS-I/O that consists of linear equivalent circuit and current sources. This paper modifies the macro-model by adding another current source to express the short-circuit current in the inverter. The macro-model was determined from SPICE calculations of impedance and power current by using a device model of an inverter IC. The modified model was tested with several load capacitances in SPICE simulation. The results showed that the macro-model predicts the power current with good accuracy in the range up to 3 GHz except for frequencies at which inductances of the package and of traces on printed circuit board and capacitance of the load caused resonances.
- リンク情報
- ID情報
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- Web of Science ID : WOS:000263416300103