MISC

2008年9月22日

Interleaved pixel lookup for embedded computer vision

2008 IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, CVPR Workshops
  • Kota Yamaguchi
  • ,
  • Yoshihiro Watanabe
  • ,
  • Takashi Komuro
  • ,
  • Masatoshi Ishikawa

DOI
10.1109/CVPRW.2008.4563152

This paper describes an in-depth investigation and implementation of interleaved memory for pixel lookup operations in computer vision. Pixel lookup, mapping between coordinates and pixels, is a common operation in computer vision, but is also a potential bottleneck due to formidable bandwidth requirements for real-time operation. We focus on the acceleration of pixel lookup operations through parallelizing memory banks by interleaving. The key to applying interleaving for pixel lookup is 2D block data partitioning and support for unaligned access. With this optimization of interleaving, pixel lookup operations can output a block of pixels at once without major overhead for unaligned access. An example implementation of our optimized interleaved memory for affine motion tracking shows that the pixel lookup operations can achieve 12.8 Gbps for random lookup of a 4×4 size block of 8-bit pixels under 100 MHz operation. Interleaving can be a cost-effective solution for fast pixel lookup in embedded computer vision. © 2008 IEEE.

リンク情報
DOI
https://doi.org/10.1109/CVPRW.2008.4563152
URL
https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=51849132753&origin=inward
ID情報
  • DOI : 10.1109/CVPRW.2008.4563152
  • SCOPUS ID : 51849132753

エクスポート
BibTeX RIS