MISC

2007年9月27日

Design of a massively parallel vision processor based on multi-SIMD rchitecture

Proceedings - IEEE International Symposium on Circuits and Systems
  • Kota Yamaguchi
  • ,
  • Yoshihiro Watanabe
  • ,
  • Takashi Komuro
  • ,
  • Masatoshi Ishikawa

開始ページ
3498
終了ページ
3501

Increasing demands for robust image recognition systems require vision processors not only with enormous computational capacities but also with sufficient flexibility to handle highly complicated recognition tasks. We describe a multi-SIMD architecture and the design of a vision processor based on it for carrying out such difficult image recognition tasks. The proposed architecture consists of two SIMD parallel processing modules and a shared memory, allowing highly parallelized and flexible computation of complicated recognition tasks, which were difficult to process on a conventional massively parallel SIMD architecture. We designed a prototype vision processor for evaluation purposes and confirmed that the processor could be implemented in FPGA. © 2007 IEEE.

リンク情報
URL
https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=34548847189&origin=inward
ID情報
  • ISSN : 0271-4310
  • SCOPUS ID : 34548847189

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