Morihiro Kuga

Profile Information

Affiliation: Kumamoto University

Degree: 博士(工学)(九州大学)

J-GLOBAL ID: 200901027861955714
researchmap Member ID: 1000253111

External link: http://www.arch.cs.kumamoto-u.ac.jp/~kuga/

Research Interests

Research Areas

Education

- 1992

Kyushu University
- 1992

Graduate School, Division of Integrated Science and Engineering, Kyushu University
- 1987

Faculty of Engineering, Fukuoka University
- 1987

Faculty of Engineering, Fukuoka University

Committee Memberships

Awards

Jun, 2017

Best Poster Award, High-level Synthesis based on Parallel Design Patterns using a Functional Language, HEART2017

M.Kuga, K.Fukuda, M.Amagasaki, M.Iida, T.Sueyoshi
Jun, 2015

優秀論文賞, Fault-tolerant FPGA: Architectures and design for Programmable Logic Intellectual Property Core in SoC, 優秀論文賞

Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
Jun, 2015

優秀論文賞, システムLSI搭載FPGA-IPコア向け物理故障検出および回避方法, 電子情報通信学会

尼崎太樹, 西谷祐樹, 井上万輝, 飯田全広, 久我守弘, 末吉敏則
2004

第11回FPGA/PLD Design Conference ユーザプレゼンテーション優秀論文賞
2002

2002年第4回 IPデザインアワード開発助成部門開発奨励賞
2002

FPGA/PLD Design Conference 優秀論文賞
2000

2000年第2回 IPデザインアワード IP優秀賞
1992

平成3年度情報処理学会論文賞

Papers

Streaming Accelerator Design for Regular Expression on CPU+FPGA Embedded System

Hendarmawan, Morihiro Kuga, Masahiro Iida

ECTI Transactions on Computer and Information Technology (ECTI-CIT), 16(4) 448-459, Oct 11, 2022
An eFPGA Generation Suite with Customizable Architecture and IDE

KUGA Morihiro, ZHAO Qian, NAKAZATO Yuya, AMAGASAKI Motoki, IIDA Masahiro

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, advpub, 2022
Automation of Domain-specific FPGA-IP Generation and Test

Yuya Nakazato, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga

Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Jun 21, 2021
Translation Rules of Regular Expression Code for Hardware Accelerator

Hendar mawan, Morihiro Kuga, Masahiro Iida

Proceedings of Asia Pacific Conference on Robot IoT System Development and Platform, (2020) 51-58, Mar 15, 2021 Peer-reviewed
Characteristic Similarity Using Classical CNN Model

Mery DIana, Juntaro Chikama, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga

34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019, Jun, 2019 Peer-reviewed
Performance Evaluation of Fine-grained Virtual FPGA Based on SLM Architecture

Theingi. Mint, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga

Proc. of IEEE Symposium on COOL Chips 22, Apr, 2019 Peer-reviewed
HCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds

Qian Zhao, Hendarmawan, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

2017 International Conference on Field-Programmable Technology, ICFPT 2017, 2018-January 267-270, Feb 2, 2018 Peer-reviewed
Enabling FPGA-as-a-service in the cloud with hCODE platform

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IEICE Transactions on Information and Systems, E101D(2) 335-343, Feb, 2018 Peer-reviewed
Low-Cost Hardware that Accelerates Frequent Item Counting with an FPGA

Gololo Doctor, Hendarmawan, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IEIE Transactions on Smart Processing and Computing, 6(5) 347-354, Oct, 2017 Peer-reviewed
High-Performance Data Filtering Processor Design for Database Acceleration using HLS

Hiroki Nakagawa, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proc. of 2017 Joint Conference of Electrical, Electronics and Information Engineers in Kyusyu, 09-1P-01-09-1P-01, Sep, 2017 Peer-reviewed
High-level Synthesis based on Parallel Design Patterns using a Functional Language

Morihiro Kuga, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi

ACM International Conference Proceeding Series, 23:1-23:6, Jun 7, 2017 Peer-reviewed
FPGA based ASIC Emulator with High Speed Optical Serial Links

Motoki Amagasaki, Futoshi Murase, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi

ACM International Conference Proceeding Series, 18:1-18:6, Jun 7, 2017 Peer-reviewed
hCODE: An open-source platform for FPGA accelerators

Qian Zhao, Takuya Nakamichi, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Proceedings of the 2016 International Conference on Field-Programmable Technology, FPT 2016, 205-208, May 15, 2017 Peer-reviewed
Physical fault detection and recovery methods for system-LSI loaded FPGA-IP core

Motoki Amagasaki, Yuki Nishitani, Kazuki Inoue, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IEICE Transactions on Information and Systems, E100D(4) 633-644, Apr, 2017 Peer-reviewed
Towards Open-HW: A platform to design, share and deploy FPGA accelerators in low cost

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IPSJ Transactions on System LSI Design Methodology, 10 63-70, 2017 Peer-reviewed
A Study of HW/SW Co-design Framework based on the Virtualization Technology

Hendarmawan, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Asia Pasific Advanced Network Conference (APAN 42), August 2016, Aug, 2016 Peer-reviewed
A Novel Soft Error Tolerant FPGA Architecture

M.Amagasaki, Y.Nakamura, M.Iida, M.Kuga, T.Sueyoshi

Proc. of IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 4a-3, Sep. 2016, 2016 Peer-reviewed
A Study of Heterogeneous Computing Design Method based on Virtualization Technology.

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

SIGARCH Computer Architecture News, 44(4) 86-91, 2016 Peer-reviewed
Theorem-proving verification for asynchronous circuits

Shunji Nishimura, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi

International Journal of Innovative Computing, Information and Control, 12(3) 761-778, 2016 Peer-reviewed
Evaluation of fault tolerant technique based on homogeneous FPGA architecture

Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, 07-10-October-2012 225-230, Nov 18, 2015 Peer-reviewed

Misc.

296

A Chip Testing Methodology for RISC-V SoC Using Jupyter Notebook

小島拓也, 小島拓也, 亀井愛佳, 矢内洋祐, 天野英晴, 久我守弘, 飯田全広

情報処理学会研究報告(Web), 2023(ARC-252), 2023
RISC-V MPおよびSLM再構成ロジックを混載した「SLMLET」チップの電力評価

矢内洋祐, 小島拓也, 小島拓也, 奥原颯, 天野英晴, 久我守弘, 飯田全広

電子情報通信学会技術研究報告(Web), 123(145(CPSY2023 8-26)), 2023
Configuration Data Compression for SLM Fine-grained Reconfigurable Logic

高木颯平, 小島拓也, 天野英晴, 久我守弘, 飯田全広

電子情報通信学会技術研究報告(Web), 123(258(VLD2023 30-79)), 2023
FPGAとRISC-Vプロセッサを搭載したSoC向けHW/SW設計フローと実機評価

小島拓也, 矢内洋祐, 奥原颯, 天野英晴, 久我守弘, 飯田全広

電子情報通信学会技術研究報告(Web), 123(191(RECONF2023 19-32)), 2023
The Verification of an FPGA-IP prototype chip for MEC Devices

久我守弘, 中里優弥, ZHAO Qian, 尼崎太樹, 飯田全広

電子情報通信学会大会講演論文集(CD-ROM), 2022, 2022
SLM based FPGA-IP soft core

中里優弥, 古賀大顕, ZHAO Qian, 尼崎太樹, 久我守弘, 飯田全広

電子情報通信学会技術研究報告(Web), 120(337(VLD2020 39-66)), 2021
社会人リカレント教育enPiT-everiにおける熊本大学の取り組み

久我守弘, 末吉敏則, 中武繁寿

Jun, 2019 Peer-reviewedLead author
小中学生を対象としたロボット・プログラミング教育とコンテストの実施

前原栄輔, 菅原智裕, 久我守弘

Jun, 2019 Peer-reviewedLast author
A case study of an FPGA implementation for streaming data filtering

中川裕貴, 堤泰卓, 久我守弘, 尼崎太樹, 飯田全広, 末吉敏則

電子情報通信学会技術研究報告, 119(18(RECONF2019 1-19)(Web)) 41‐46 (WEB ONLY), May 2, 2019
A case study of database filtering on streaming processing

中川裕貴, 久我守弘, 尼崎太樹, 飯田全広, 末吉敏則

電子情報通信学会技術研究報告, 118(215(RECONF2018 19-33)(Web)) 79‐84 (WEB ONLY), Sep 10, 2018
A Case Study on Complex Event Processing over low cost ARM+FPGA Boards

Hendarmawan, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

118(215) 13-18, Sep, 2018
Visibility study of CNN implementation using High Speed Serial Optical Interconnection

千竈純太郎, 中原康宏, 尼崎太樹, 久我守弘, 飯田全広, 末吉敏則

電子情報通信学会技術研究報告, 118(63(RECONF2018 1-18)(Web)) 33‐38 (WEB ONLY), May 17, 2018
FPGAの高速シリアル通信を用いたクラスタコンピューティング環境の一検討

高木大智, 趙謙, 久我守弘, 尼崎太樹, 飯田全広, 末吉敏則

情報処理学会九州支部火の国情報シンポジウム2018, (A6-1) 1-6, Mar, 2018
FPGA accelerator of CNN using Power of 2 Approximation and Pruning weights

宇都宮誉博, 尼崎太樹, 飯田全広, 久我守弘, 末吉敏則

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 117(377) 119-124, Jan 18, 2018
High-level synthesis from a functional language focused on higher-order functions

Record of Joint Conference of Electrical and Electronics Engineers in Kyushu, 2018 248-249, 2018
CNN implementation using High Speed Optical Serial Links

Record of Joint Conference of Electrical and Electronics Engineers in Kyushu, 2018 251-251, 2018
CNN accerarator using power-of-two weight and pruning

Record of Joint Conference of Electrical and Electronics Engineers in Kyushu, 2018 250-250, 2018
Performance Evaluation Three Dimensional FPGA Architecture with Face-down Stacking

明石啓司郎, 尼崎太樹, 趙謙, 飯田全広, 久我守弘, 末吉敏則

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 117(279) 31-36, Nov 6, 2017
A Study on Graph Processing by Stream Using FPGA

松崎貴之, 尼崎太樹, 飯田全広, 久我守弘, 末吉敏則

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 117(279) 7-12, Nov 6, 2017
hCODE 2.0 : An Open-source Platform for FPGA Cluster System

中川裕貴, 趙謙, 尼崎太樹, 飯田全広, 久我守弘, 末吉敏則

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 117(273) 1-6, Nov 6, 2017

Books and Other Publications

リコンフィギャラブルシステム

末吉敏則, 天野英晴 (Role: Joint author, ３章)

オーム社, 2005 (ISBN: 427420071X)

Presentations

A Case Study Implementation of Saliency Detection Based on SBD Method -Improving the Detection Accuracy with CIELUV Color Space-

Ryuichi Hashimoto, Morihiro Kuga

Joint Conference of Electrical, Electronics and Information Engineers in Kyusyu, Oct 17, 2022
A Case Study Implementation of Saliency Detection Based on SBD Method - FPGA acceleration of Mahalanobis Distance Calculation

Mai Enokizono, Ryuichi Hashimoto, Morihiro Kuga

Joint Conference of Electrical, Electronics and Information Engineers in Kyusyu, Sep 17, 2022
FPL Demo: An FPGA-IP Prototype Chip for MEC devices

Morihiro Kuga, Masahiro Iida, Hideharu Amano

International Conference on Field Programmable Logic and Applications (FPL2022), Aug 31, 2022
パイプライン動作する演算モジュールのRTL記述から動作記述への抽象化

高木彬, 久我守弘, 飯田全広, 伊藤寛人, 井戸大介

火の国情報シンポジウム2022, Mar 2, 2022
RTL記述から動作記述への抽象化における組合せ回路の解析フロー

安楽亮大郎, 久我守弘, 伊藤寛人, 井戸大介, 飯田全広

火の国情報シンポジウム2021, Mar 2, 2021
2のべき乗近似とプルーニングを用いたCNN向けFPGAアクセラレータ

宇都宮誉博, 尼崎太樹, 飯田全広, 久我守弘, 末吉敏則

電子情報通信学会技術研究報告, Jan 11, 2018
FPGAを用いたグラフストリーム処理の一検討

松崎貴之, 尼崎太樹, 飯田全広, 久我守弘, 末吉敏則

電子情報通信学会技術研究報告, Oct 30, 2017
hCODE2.0:FPGAクラスタシステム向けオープンソース開発管理プラットフォーム

中川裕貴, ZHAO Qian, 尼崎太樹, 飯田全広, 久我守弘, 末吉敏則

電子情報通信学会技術研究報告, Oct 30, 2017
Face‐down積層型3次元FPGAの性能評価

明石啓司郎, 尼崎太樹, ZHAO Qian, 飯田全広, 久我守弘, 末吉敏則

電子情報通信学会技術研究報告, Oct 30, 2017
関数型言語における高階関数を利用した高位合成の一検討

寺岡拓也, 久我守弘, 尼崎太樹, 飯田全広, 末吉敏則

電子情報通信学会技術研究報告, Sep 18, 2017
熊本大学における集積回路設計教育の変遷と現状

末吉敏則, 久我守弘

電気学会電子・情報・システム部門大会講演論文集(CD-ROM), Sep 6, 2017
任意精度演算可能なビットシリアル演算器の提案

三浦巴慎, 尼崎太樹, 飯田全広, 久我守弘, 末吉敏則

電子情報通信学会技術研究報告, May 15, 2017
重みの2のべき乗近似を用いたCNNのFPGA実装に関する一検討

宇都宮誉博, 尼崎太樹, 飯田全広, 久我守弘, 末吉敏則

電子情報通信学会技術研究報告, May 15, 2017
高速シリアル光インターコネクトを用いたFPGA分割実装

村瀬大, 高木大智, 尼崎太樹, 久我守弘, 飯田全広, 末吉敏則

電子情報通信学会技術研究報告, Jan 16, 2017
3次元FPGA向け消費電力解析ツール

池邊雅登, ZHAO Qian, 尼崎太樹, 飯田全広, 久我守弘, 末吉敏則

電子情報通信学会技術研究報告, Nov 21, 2016
Super KITEとシステムレベル設計教材

第13回FPGA/PLD Design Conference IPフリーマーケットin EDSFair2006投稿IPカタログ, 2006
リモート・ロジックアナライザの実装と評価

2006
FPGA遠隔再構成環境におけるBuilt-In Self Test機構

2006
リコンフィギャラブルシステムと遠隔再構成技術

Electronic Design and Solution Fair 2005 ユニバーシティ・プラザ大学研究室による研究発表資料集, 2006
CPU混載部分再構成型FPGAを用いた動的再構成システムの開発

第13回FPGA/PLD Design Conference ユーザプレゼンテーション論文集, 2006

Professional Memberships

Works

Research Projects

Research and Development of High-speed Logic Emulator for Ultra-Scale Integrated Circuit

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (C), Japan Society for the Promotion of Science, Apr, 2016 - Mar, 2019

Kuga Morihiro, ZHAO Qian, AMAGASAKI Motoki, IIDA Masahiro, SUEYOSHI Toshinori
Development of Self-Repair Dependable system on FPGA

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 2010 - 2012

SUEYOSHI Toshinori, KUGA Morihiro, AMAGASAKI Motoki
Research and development of OS functions for reconfigurable systems to improve their availability

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (C), Japan Society for the Promotion of Science, 2009 - 2011

KUGA Morihiro, TSUTSUMI Yoshiaki, TOMONAGA Kenji, USAGAWA Sadaki, SAEKI Ryosuke, TAKAHASHI Katsunori, UDA Takashige
Research for Reconfigurable System Technology using Fine Grained Cell Architecture

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 2005 - 2007

SUEYOSHI Toshinori, KUGA Morihiro
Research and Development of Flexible Hardware and Remote Reconfiguration Techniques

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 2002 - 2004

SUEYOSHI Toshinori, KUGA Morihiro, SHIBAMURA Hidetomo
Study on Next Generation FPGA toward Reconfigurable Computing

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 1999 - 2001

SUEYOSHI Toshinori, SHIROUZU Hiroshi, SHIBAMURA Hidetomo, KUGA Morihiro
Study of Reconfigurable Processor using Programmable LSI

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (C), Japan Society for the Promotion of Science, 1997 - 1998

SUEYOSHI Toshinori, NAKASHIMA Takuo, SHIBAMURA Hidetomo, KUGA Morihiro
Rapid Prototyping Technology for Large Scale Logic Circuits

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Japan Society for the Promotion of Science, 1997 - 1998

SUEYOSHI Toshinori, SHIROUZU Hiroshi, SHIBAMURA Hidetomo, SASAKI Mamoru, KUGA Morihiro
再構成型機能装置付き計算機のためのプログラミング支援ツールに関する研究

科学研究費助成事業, 奨励研究(A), 日本学術振興会, 1996 - 1996

久我守弘
Study of Cluster Computing on a High Speed Network Environment

Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (C), Japan Society for the Promotion of Science, 1995 - 1996

SUEYOSHI Toshinori, OHNISHI Yoshimasa, APDUHAN Bernady, KUGA Morihiro
超並列計算機のための運転監視機構に関する研究

科学研究費助成事業, 奨励研究(A), 日本学術振興会, 1994 - 1994

久我守弘
Study on Interconnection Networks Towards Realization of a Reconfigurable Parallel Computer

Grants-in-Aid for Scientific Research, Grant-in-Aid for General Scientific Research (C), Japan Society for the Promotion of Science, 1993 - 1994

SUEYOSHI Toshinori, TANAKA Koichiro, APDUHAN Bernady, KUGA Morihiro
機械命令レベル並列処理プロセッサの設計支援環境に関する研究

科学研究費助成事業, 奨励研究(A), 日本学術振興会, 1993 - 1993

久我守弘
計算機システムの高速化に関する研究
ハードウェア/ソフトウェア・コデザインに関する研究
リコンフィギャラブル・コンピューティング・システムに関する研究
A study for high performance ｃｏｍｐｕｔｅｒ architectures
A study for Hardware/Software codesign
A study for Reconfigurable Computiug Systems

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Misc.

Books and Other Publications

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