2013年2月1日
ΔΣ型分数分周PLLのセルフディザリング手法の検討
電気学会論文誌. C, 電子・情報・システム部門誌 = The transactions of the Institute of Electrical Engineers of Japan. C, A publication of Electronics, Information and Systems Society
- ,
- ,
- 巻
- 133
- 号
- 2
- 開始ページ
- 234
- 終了ページ
- 238
- 記述言語
- 日本語
- 掲載種別
- 研究論文(学術雑誌)
- DOI
- 10.1541/ieejeiss.133.234
- 出版者・発行元
- 一般社団法人 電気学会
The ΔΣ fractional-N PLL is been researched to realize a low fractional spurious signal characteristic. In this PLL, the ΔΣ modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the ΔΣ modulator when the input value is fixed. As a result, the limit cycle oscillation increases a spurious signal power. Therefore, some method is required for suppressing this oscillation. In this paper, we propose a self-dithering ΔΣ fractional-N PLL that inhibits the limit cycle oscillation without the external dither generating circuit. The proposed circuit generates the dither from internal signals of PLL. We simulated the output spectrum of the proposed circuit. As a result, we show that the proposed circuit suppressed the limit cycle oscillation, and that the spurious level of the proposed circuit was almost equals to a spurious level without the limit cycle oscillation.
- リンク情報
- ID情報
-
- DOI : 10.1541/ieejeiss.133.234
- ISSN : 0385-4221
- eISSN : 1348-8155
- CiNii Articles ID : 10031142430
- CiNii Books ID : AN10065950
- CiNii Research ID : 1390001204608407808
- SCOPUS ID : 84874168828