宇賀神 守

A study of phase-adjusting architectures for low-phase-noise quadrature voltage-controlled oscillators 

IEICE Transactions on Electronics E106C(2) 59-66 2023年2月  査読有り筆頭著者責任著者

A quadrature voltage-controlled oscillator using phase-adjusting architecture for suppressing phase noise 

IEICE Electronics Express 18(10) 2021年5月  査読有り筆頭著者責任著者

An (n + n^2)-mixer architecture for a high-image-rejection wireless receiver with an n-phase active complex filter 

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E100A(4) 1008-1014 2017年4月  査読有り筆頭著者責任著者

High-image-rejection wireless-receiver architecture with a 3-phase active RC complex filter 

IEICE Electronics Express 12(12) 2015年6月  査読有り筆頭著者責任著者

Proposal of channel-grouping wireless-transceiver architecture for suppressing local-oscillator phase noise 

IEICE Electronics Express 9(2) 86-91 2012年1月  査読有り筆頭著者責任著者

Operation of ultra-low leakage regulator circuits with SOI and bulk technologies for controlling wireless transceivers 

IEICE Transactions on Electronics E94C(10) 1702-1705 2011年10月  査読有り筆頭著者責任著者

Design and performance of a sub-nano-ampere two-stage power management circuit in 0.35-μm CMOS for dust-size sensor nodes 

IEICE Transactions on Electronics E94-C(7) 1206-1211 2011年7月  査読有り筆頭著者責任著者

A 1-V CMOS SOI Bluetooth RF transceiver using LC-tuned and transistor-current-source folded circuits 

IEEE Journal of Solid-State Circuits 39(4) 569-576 2004年4月  査読有り筆頭著者責任著者

A 1-V CMOS/SOI bluetooth RF transceiver for compact mobile applications 

Symposium on VLSI Circuits 123-126 2003年  査読有り筆頭著者責任著者

A 0.6-V supply, voltage-reference circuit based on threshold-voltage-summation architecture in fully-depleted CMOS/SOI 

IEICE Transactions on Electronics E85C(8) 1588-1595 2002年8月  査読有り筆頭著者責任著者

A 1-V 2-GHz RF receiver with 49 dB of image rejection in CMOS/SIMOX 

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E85A(2) 293-299 2002年2月  査読有り筆頭著者責任著者

A 0.6-V voltage reference circuit based on Σ-VTH architecture in CMOS/SIMOX 

Symposium on VLSI Circuits 141-142 2001年6月  査読有り筆頭著者責任著者

A 1 V 12 mW 2 GHz receiver with 49 dB image rejection in CMOS/SIMOX, 

IEEE International Conference on Solid-State Circuits (ISSCC) 288-289 2001年2月  査読有り筆頭著者責任著者

Very-high fT and fmax silicon bipolar transistors using ultra-high-performance super self-aligned process technology for low-energy and ultra-high-speed LSI's 

IEEE International Electron Devices Meeting (IEDM) 735-738 1995年12月  査読有り筆頭著者責任著者

Significant time constants defined by high-current charge dynamics in advanced silicon-based bipolar transistors 

IEEE Transactions on Electron Devices ED-4(10) 1796-1800 1994年10月  査読有り筆頭著者責任著者

SiGe drift base bipolar transistor with self-aligned selective CVD-tungsten electrodes 

IEEE Transactions on Electron Devices 41(3) 427-432 1994年3月  査読有り筆頭著者責任著者

A simulation study of high-speed silicon heteroemitter bipolar transistors 

IEEE Transactions on Electron Devices 36(6) 1102-1109 1989年6月  査読有り筆頭著者責任著者