2004年
Performance limitation of on-chip global interconnects for high-speed signaling
PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE
- ,
- ,
- ,
- 開始ページ
- 489
- 終了ページ
- 492
- 記述言語
- 英語
- 掲載種別
- 出版者・発行元
- IEEE
This paper discusses performance limitation of on-chip interconnects. On-chip global interconnects are considered to be a bottleneck of high-performance LSIs. To overcome this issue, high-speed signaling and large throughput interconnection using electrical wires are studied. However the limitation of on-chip interconnects has not been studied sufficiently. This paper reveals the maximum performance of on-chip global interconnects based on derived analytic expressions and detailed circuit simulation. We derive trade-off curves among bit rate, interconnect length, and eye opening both for single-end and for differential signaling. The results show that differential signaling improves signaling performance several times compared with conventional single-end signaling, and demonstrate that 80 Gbps differential signaling on 10mm interconnects is promising.
- リンク情報
- ID情報
-
- Web of Science ID : WOS:000224961000099