論文

2000年12月

A performance optimization method by gate resizing based on statistical static timing analysis

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
  • M Hashimoto
  • ,
  • H Onodera

E83A
12
開始ページ
2558
終了ページ
2568
記述言語
英語
掲載種別
研究論文(学術雑誌)
出版者・発行元
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

This paper discusses a Rate resizing method for performance enhancement based on statistical static timing analysis. The proposed method focuses oil timing uncertainties caused by local random fluctuation. Our method aims to remove both over-design and under-design of a circuit, and realize highperformance and high-reliability LSI design. The effectiveness of our method is examined by 6 benchmark circuits. We verify that our method ran reduce the delay time further from the circuits optimized for minimizing the delay without the consideration of delay fluctuation.

リンク情報
Web of Science
https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:000166143800021&DestApp=WOS_CPL
ID情報
  • ISSN : 0916-8508
  • eISSN : 1745-1337
  • Web of Science ID : WOS:000166143800021

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