2005年12月
On-chip Thermal Gradient Analysis and Temperature Flattening for SoC Design
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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- 巻
- E88-A
- 号
- 12
- 開始ページ
- 3382
- 終了ページ
- 3389
- 記述言語
- 英語
- 掲載種別
- DOI
- 10.1093/ietfec/e88-a.12.3382
- 出版者・発行元
- 一般社団法人電子情報通信学会
This paper quantitatively analyzes thermal gradient of SoC and proposes a thermal flattening procedure. First, the impact of dominant parameters, such as area occupancy of memory/logic block, power density, and floorplan on thermal gradient are studied quantitatively. Temperature difference is also evaluated from timing and reliability standpoints. Important results obtained here are 1) the maximum temperature difference increases with higher memory area occupancy and 2) the difference is very floorplan sensitive. Then, we propose a procedure to amend thermal gradient. A slight floorplan modification using the proposed procedure improves on-chip thermal gradient significantly.
- リンク情報
- ID情報
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- DOI : 10.1093/ietfec/e88-a.12.3382
- ISSN : 0916-8508
- CiNii Articles ID : 110004019440
- CiNii Books ID : AA10826239