2005年12月
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance.
IEICE Transactions
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- 巻
- 88-A
- 号
- 12
- 開始ページ
- 3453
- 終了ページ
- 3462
- 記述言語
- 英語
- 掲載種別
- 研究論文(学術雑誌)
- DOI
- 10.1093/ietfec/e88-a.12.3453
- 出版者・発行元
- 一般社団法人電子情報通信学会
Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2-10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas. Copyright © 2005 The Institute of Electronics, Information and Communication Engineers.
- リンク情報
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- DOI
- https://doi.org/10.1093/ietfec/e88-a.12.3453
- DBLP
- https://dblp.uni-trier.de/rec/journals/ieicet/KurokawaHKHYIIM05
- CiNii Articles
- http://ci.nii.ac.jp/naid/110004019449
- CiNii Books
- http://ci.nii.ac.jp/ncid/AA10826239
- URL
- http://dblp.uni-trier.de/db/journals/ieicet/ieicet88a.html#journals/ieicet/KurokawaHKHYIIM05
- ID情報
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- DOI : 10.1093/ietfec/e88-a.12.3453
- ISSN : 0916-8508
- DBLP ID : journals/ieicet/KurokawaHKHYIIM05
- CiNii Articles ID : 110004019449
- CiNii Books ID : AA10826239
- SCOPUS ID : 29144493232