2011年
Power Gating Implementation for Noise Mitigation with Body-Tied Triple-Well Structure
2011 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC)
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- 記述言語
- 英語
- 掲載種別
- 研究論文(国際会議プロシーディングス)
- 出版者・発行元
- IEEE
This paper investigates power gating implementations that mitigate power supply noise. We focus on the body connection of power-gated circuits, and examine the amount of power supply noise induced by power-on rush current and the contribution of a power-gated circuit as a decoupling capacitance during the sleep mode. To figure out the best implementation, we designed and fabricated a test chip in 65nm process. Experimental results with measurement and simulation reveal that the power-gated circuit with body-tied structure in triple-well is the best implementation from the following three points; power supply noise due to rush current, the contribution of decoupling capacitance during the sleep mode and the leakage reduction thanks to power gating.
- リンク情報
- ID情報
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- Web of Science ID : WOS:000296981700049