2008年12月
Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
- ,
- ,
- 巻
- E91A
- 号
- 12
- 開始ページ
- 3481
- 終了ページ
- 3487
- 記述言語
- 英語
- 掲載種別
- 研究論文(学術雑誌)
- DOI
- 10.1093/ietfec/e91-a.12.3481
- 出版者・発行元
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Influence of manufacturing variability on circuit performance has been increasing because of finer manufacturing process and lowered supply voltage. In this paper, we focus on mesh-style clock distribution which is believed to be effective for reducing clock skew, and we evaluate clock skew considering manufacturing and design variabilities. Considering MOS transistor variation-random and spatially-correlated variation - and non-uniform flip-flop (FF) placement, we demonstrate that spatially-correlated variation and severe non-uniform FF distribution can be major sources of clock skew. We also examine the dependency of clock skew on design parameters, and reveal that finer clock mesh does not necessarily reduce clock skew.
- リンク情報
- ID情報
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- DOI : 10.1093/ietfec/e91-a.12.3481
- ISSN : 1745-1337
- Web of Science ID : WOS:000262164800010