2008年
Measurement of Supply Noise Suppression by Substrate and Deep N-well in 90nm Process
2008 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE
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- 開始ページ
- 393
- 終了ページ
- 396
- 記述言語
- 英語
- 掲載種別
- 研究論文(国際会議プロシーディングス)
- 出版者・発行元
- IEEE
This paper measures and compares power supply and ground noises in a triple-well structure and a twin-well stricture. The measurement results of power supply and ground waveforms in a 90nm CMOS process reveal that the power noise reduction thanks to the increased junction capacitance associated with the triple-well structure overwhelms the ground noise suppression due to the resistive network of p-substrate in the twin-well structure. These noise suppression effects are well correlated with the simulation that uses on-chip RC power distribution model with package inductance, chip-level p-substrate resistive mesh and distributed well junction capacitances.
- リンク情報
- ID情報
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- Web of Science ID : WOS:000265155300099