論文

査読有り
2015年10月9日

Multi-level queue NVM/DRAM hybrid memory management with language runtime support

Proceeding of the 2015 Research in Adaptive and Convergent Systems, RACS 2015
  • Gaku Nakagawa
  • ,
  • Shuichi Oikawa

開始ページ
437
終了ページ
442
記述言語
英語
掲載種別
研究論文(国際会議プロシーディングス)
DOI
10.1145/2811411.2811531
出版者・発行元
Association for Computing Machinery, Inc

Non-volatile memory devices (NVM) devices, such as PCM, STT-MRAM, and ReRAM, enable the integration of secondary storage into main memory. This integration reduces I/O access to slow block devices
however, it is currently unrealistic to construct a large capacity main memory with a single NVM, because such devices have certain write access limitations. Combining NVM and other memory devices is necessary to overcome such disadvantages. Several researches discussed NVM/DRAM hybrid memory, combining NVM and DRAM. To use NVM/DRAM hybrid memory, the placement of data between NVM and DRAM must be determined. In particular, write-hot data should be allocated to DRAM and write-cold data to NVM. For data placement, programming language runtime supports are useful because they possess more detailed information about write access than the operating systems. A previous research proposed the individual counting method to manage NVM/DRAM hybrid memory with programming language runtime support that determine data placement based on the number of write accesses to each object. However, it is difficult to determine dynamically threshold values for data placements using the individual counting method. Here we propose a multi-level queue method to distinguish between write-hot and write-cold data. Experimental results show that the proposed method resolves the limitations of the individual counting method.

リンク情報
DOI
https://doi.org/10.1145/2811411.2811531
ID情報
  • DOI : 10.1145/2811411.2811531
  • SCOPUS ID : 84960865569

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