2008年6月
Design of low power track and hold circuit based on two stage structure
IEICE TRANSACTIONS ON ELECTRONICS
- ,
- ,
- ,
- 巻
- E91C
- 号
- 6
- 開始ページ
- 894
- 終了ページ
- 902
- 記述言語
- 英語
- 掲載種別
- DOI
- 10.1093/ietele/e91-c.6.894
- 出版者・発行元
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
This paper proposes a low power and high speed track and hold circuit (T/H circuit) based on the two-stage structure. The proposed circuit consists of two internal T/H circuits connected in cascade. The first T/H circuit converts an input signal into a step voltage and it is applied to the following second T/H circuit which drives large load capacitors and consumes large power. Applying the step voltage to the second T/H circuit prevents the second T/H circuit from charging and discharging its load capacitor during an identical track phase and enables low power operation. Thanks to the two-stage structure the proposed T/H circuit can save 29% of the power consumption compared with the conventional one. An optimum design procedure of the proposed two stage T/H circuit is explained and its validity is confirmed by HSPICE simulations.
- リンク情報
- ID情報
-
- DOI : 10.1093/ietele/e91-c.6.894
- ISSN : 0916-8524
- eISSN : 1745-1353
- Web of Science ID : WOS:000256861800011