TAKEUCHI Yoshinori

J-GLOBAL         Last updated: Feb 15, 2019 at 13:36
 
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Name
TAKEUCHI Yoshinori
Affiliation
Kindai University
Section
Faculty of Science and Engineering Department of Electric and Electronic Engineering
Job title
Associate Professor
Degree
(BLANK)(Tokyo Institute of Technology), (BLANK)(Tokyo Institute of Technology)

Research Areas

 
 

Academic & Professional Experience

 
1996
 - 
1999
: Osaka University, Assistant Professor,  
 

Education

 
 
 - 
1992
Graduate School, Division of Science and Engineering, Tokyo Institute of Technology
 
 
 - 
1987
Faculty of Engineering, Tokyo Institute of Technology
 

Awards & Honors

 
2011
The IEEK Semiconductor & Device Society paper award, The Institute of Electronics Engineers of Korea
Winner: Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, and Masaharu Ima
 
2010
IEEE Solid-State Circuits Society Japan Chapter Academic Research Award
 
2010
IEEE Solid-State Circuits Society Japan Chapter Academic 0Research Award, IEEE Solid-State Circuits Society Japan Chapter
Winner: Hiroki Osawa, Hirofumi Iwato, Kanehiro Kondo, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai, Akira Matsuzawa, Yoshihiko Hirao
 
2009
IEICE Senior Member
 

Published Papers

 
Phase Locking Value Calculator based on Hardware-oriented Mathematical Expression
Tomoki Sugiura, Jaehoon Yu, Yoshinori Takeuchi
IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences   E101-A(12) 2254-2261   Dec 2018   [Refereed]
Decomposed Vector Histograms of Oriented Gradients for Efficient Hardware Implementation
Koichi Mitsunari, Yoshinori Takeuchi, Masaharu Imai, Jaehoon Yu
IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences   E101-A(11) 1766-1775   Nov 2018   [Refereed]
Performance Analysis of Temporal Codings for Spiking Neural Network
Kenshi Ito and Yoshinori Takeuchi
The 21st Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2018)   14-19   Mar 2018   [Refereed]
Tomoki Sugiura, Jaehoon Yu, and Yoshinori Takeuchi,
IEEE Biomedical Circuits and Systems Conference 2017 (BioCAS 2017)   416-419   Sep 2017   [Refereed]
and Application Program Developing Environment
Yusuke Hyodo,Kensuke Murata,Takuji Hieda,Keishi Sakanushi,Yoshinori Takeuchi,and Masaharu Imai
IPSJ Symposium Series, Design Automation Symposium 2011      Sep 2011
Proposal of an Architecture Description Language for HDL Generation
Kensuke Murata,Takuji Hieda,Keishi Sakanushi,Yoshinori Takeuchi,and Masaharu Imai
IPSJ Symposium Series, Design Automation Symposium 2011      Sep 2011
A processor architecture for Multi Dimensional Parity Check code processing
Ryota Endo, Takashi Hamabe, Keishi Sakanushi, Yoshinori Takeuchi, and Masaharu Imai
IPSJ Symposium Series, Design Automation Symposium 2011      Sep 2011
Design and Evaluation of a Processor for Cyclic Code
Kazuki Ohya, Takashi Hamabe, Keishi Sakanushi, Yoshinori Takeuchi, and Masaharu Imai
Proceedings of Forum on Information Technology 2011      Sep 2011   [Refereed]
Energy Efficient Instruction-set Extension Method considering Inline Expansion
Sho Ninomiya, Keishi Sakanushi, Yoshinori Takeuchi, and Masaharu Imai
Proceedings of the 24th Workshop on Circuit and System in Awaji      Aug 2011   [Refereed]
Task Assignment Method for DVS based multiprocessor SoC
Yoshinori Takeuchi, Taichiro Shiraishi, Keishi Sakanushi, and Masaharu Imai
Proceedings of 11th International Forum on Embedded MPSoC and Multicore (MPSoC 2011)      Jul 2011   [Invited]
Electronic Triage Tag for Monitoring Casualties in the Disaster Scene
Keishi Sakanushi, Takuji Hieda, Yoshinori Takeuchi, and Masaharu Imai
Proceedings of the 26th International Technical Conference on Circuits/Systems, Computers and Communications      Jun 2011   [Refereed]
Reliable and Low Power Communication on Biomedical Information and healthcare Sensing System
Masaharu Imai, Takashi Hamabe, Yoshinori Takeuchi, and Keishi Sakanushi
Proceedings of Workshop on LSI and System 2011      May 2011   [Invited]
Low Energy Task Assignment Method for DVS based Multi-Processor System
Taichiro Shiraishi, Keishi Sakanushi, Yoshinori Takeuchi, and Masaharu Imai
IPSJ SIG Technical Report   2010(6) 1-6   Mar 2011
Electronic Triage System with Human Body Communication between Casualties and Medical Staffs
Keishi Sakanushi, Jun Suzuki, Taichiro Shiraishi, Takuji Hieda, Yoshinori Takeuchi, and Masaharu Imai
IPSJ SIG Technical Report   110(474) 165-170   Mar 2011
Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, and Hirofumi Iwato
Proceedings of the Asia and South Pacific Design Automation Conference 2011 (ASPDAC 2011)      Jan 2011   [Invited]
Reliable and Low Power Communication on Biomedical Information Sensing System
Masaharu Imai, Yoshinori Takeuchi, Takashi Hamabe, and Keishi Sakanushi
IEICE technical report      Jan 2011   [Invited]
Automatic Retargeting of Binutils and GDB Based Plug-in Method
Soichiro TAGA, Takahiro KUMURA, Nagisa ISHIURA, Yoshinori TAKEUCHI, and Masaharu IMAI
   Jan 2011
Low Energy MDPC Implementation using Special Instructions on Application Domain Specific Instruction-Set Processor
Yoshinori Takeuchi, Hiroki Ohsawa, Tomohiro Kondo, Hirofumi Iwato, Keishi Sakanushi, and Masaharu Imai
Proceedings of Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ACS 2010)      Dec 2010   [Refereed]
Yoshinori Takeuchi, Keishi Sakanushi and Masaharu Imai
Proceedings of 2010 International SoC Design Conference      Nov 2010   [Invited]
Generation Method of Decomposed Small Area Instruction Decoder for Configurable Processor
Hiroki Ohsawa, Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, and Masaharu Imai
Proceedings of The 16th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2010)      Oct 2010   [Refereed]

Misc

 
Design of application specific CISC using PEAS-III(共著)
Rapid Prototyping System 2002 (RAS2002)   pp.12-18    2002
Code Efficiency Evaluation for Embedded Processors (共著)
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E85-A No.4 pp.811-818    2002
Design Space Exploration for DSP Applications using the ASIP Development System PEAS-III (共著)
IEEE International Conference on Acoustics, Speech, and Signal Processing 2002 (ICASSP 2002)   Vol.3, pp.3168 - 3171/,    2002
Rapid Prototyping of Complex Instructions for Embedded Processors using PEAS-III(共著)
10th Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI 2001)   pp.61-66    2001
The 27th EUROMICRO Conference (EUROMICRO 2001)   pp.400-409    2001

Books etc

 
"ASIP Meister,"Processor Description Languages,Prabhat Mishra and Nikil Dutt, eds.
Yuki Kobayashi, Yoshinori Takeuchi, and Masaharu Imai (Part:Joint Work)
Springer   Jun 2008   
"Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model,"VLSI-SoC: Research Trends in VLSI and Systems on Chip,Giovanni De Micheli, Salvador Mir, Ricardo Reis, eds,
Ittetsu TANIGUCHI, Keishi SAKANUSHI, Kyoko UEDA, Yoshinori TAKEUCHI, and Masaharu IMAI (Part:Joint Work)
Springer   Dec 2007   
System Level Synthesis
Masaharu Imai, Yoshinori Takeuchi, Norimasa Ohtsuki, Nobuyuki Hikichi (Part:Joint Work)
Kluwer Academic Publishers   Aug 1999   
'Compiler Generation Techniques for Embedded Processors and thier Application to HW/SW Codesign' System Level Synthesis, (共著)
1999   
'Parallel Algorithm for Recursive Linear Filtering on Transputers', Transputing in Numerical and Neural Network Applications
Yoshinori Takeuchi, Tsuyoshi Isshiki and Hiroaki Kunieda (Part:Joint Work)
IOS Press   Dec 1992   

Conference Activities & Talks

 
Coding Analysis for Spiking Neural Network Models
TAKEUCHI Yoshinori
18th International Forum on MPSoC for Software-defined Hardware 2018   2 Aug 2018   

Works

 
HW/SW Codesign Methodology in Quarta Submicron Era.
1996 - 2000
Design Methodology for Flexible System LSI
2000
Application to Communication Systems of HW/SW Codesign
2000
Optimization for Dynamic Reconfigurable Components
2008

Research Grants & Projects

 
Study on VLSI Signal Processing
Study on VLSI Design
Study on VLSI Design Methodology
VLSI Architecture Synthesis suitable for Target Application