論文

査読有り
2015年6月

Conversion of a CMOS Logic Circuit Design to an RSFQ Design Considering Latching Function of RSFQ Logic Gates

IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY
  • Nobutaka Kito
  • ,
  • Kazuyoshi Takagi
  • ,
  • Naofumi Takagi

25
3
開始ページ
1300905
終了ページ
記述言語
英語
掲載種別
研究論文(学術雑誌)
DOI
10.1109/TASC.2014.2378593
出版者・発行元
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

A method for converting a CMOS logic circuit design to an efficient RSFQ design, which minimizes the number of flip-flops during conversion, is proposed. In an RSFQ circuit, each data input terminal of a logic gate has latching function, and the function is enabled or disabled depending on the order of the arrivals of the data pulse and the corresponding clock pulse. The number of flip-flops is minimized by the use of the latching functions through arrangement of the order of pulse arrivals of each gate and also by circuit retiming. A conversion tool based on the proposed method has been developed. Conversion results of CMOS benchmark circuits show that most of the flip-flops in the circuits are eliminated by the proposed method. A 4-bit RSFQ processor was successfully designed by an existing CMOS design tool and the developed conversion tool.

リンク情報
DOI
https://doi.org/10.1109/TASC.2014.2378593
Web of Science
https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:000211429600019&DestApp=WOS_CPL
ID情報
  • DOI : 10.1109/TASC.2014.2378593
  • ISSN : 1051-8223
  • eISSN : 1558-2515
  • Web of Science ID : WOS:000211429600019

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