論文

査読有り 招待有り
2015年6月

High-Speed Demonstration of Bit-Serial Floating-Point Adders and Multipliers Using Single-Flux-Quantum Circuits

IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY
  • Xizhu Peng
  • ,
  • Qiuyun Xu
  • ,
  • Faichi Kato
  • ,
  • Yuki Yamanashi
  • ,
  • Nobuyuki Yoshikawa
  • ,
  • Akira Fujimaki
  • ,
  • Naofumi Takagi
  • ,
  • Kazuyoshi Takagi
  • ,
  • Mutsuo Hidaka

25
3
開始ページ
1301106
終了ページ
記述言語
英語
掲載種別
研究論文(学術雑誌)
DOI
10.1109/TASC.2014.2382973
出版者・発行元
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

We have been developing a large-scale reconfigurable data path (LSRDP) based on single-flux-quantum (SFQ) circuit technology for high-performance computing systems. In the SFQ LSRDP, a large number of SFQ floating-point adders (FPAs) and floating-point multipliers (FPMs) are directly connected to each other through routing networks to reduce a memory access rate. In this paper, we show our recent results about the SFQ FPAs and FPMs. Utilization of the National Institute of Advanced Industrial Science and Technology's 10-kA/cm(2) Nb process makes it possible to accelerate the clock frequency to more than 50 GHz. We successfully demonstrated the high-speed operation of single-precision FPAs and FPMs, whose clock frequency is beyond 50 GHz, by on-chip high-speed tests. We estimate the performance and energy efficiency of SFQ FPAs and FPMs based on the designed circuits.

リンク情報
DOI
https://doi.org/10.1109/TASC.2014.2382973
Web of Science
https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:000351362200005&DestApp=WOS_CPL
ID情報
  • DOI : 10.1109/TASC.2014.2382973
  • ISSN : 1051-8223
  • eISSN : 1558-2515
  • Web of Science ID : WOS:000351362200005

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