2011年
Partial product generation utilizing the sum of operands for reduced area parallel multipliers
IPSJ Transactions on System LSI Design Methodology
- ,
- 巻
- 4
- 号
- 開始ページ
- 131
- 終了ページ
- 139
- 記述言語
- 英語
- 掲載種別
- 研究論文(学術雑誌)
- DOI
- 10.2197/ipsjtsldm.4.131
We propose a novel method to generate partial products for reduced area parallel multipliers. Our method reduces the total number of partial product bits of parallel multiplication by about half. We call partial products generated by our method Compound Partial Products (CPPs). Each CPP has four candidate values: zero, a part of the multiplicand, a part of the multiplier and a part of the sum of the operands. Our method selects one from the four candidates according to a pair of a multiplicand bit and a multiplier bit. Multipliers employing the CPPs are approximately 30% smaller than array multipliers without radix-4 Booth's method, and approximately up to 10% smaller than array multipliers with radix-4 Booth's method. We also propose an acceleration method of the multipliers using CPPs. © 2011 Information Processing Society of Japan.
- リンク情報
- ID情報
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- DOI : 10.2197/ipsjtsldm.4.131
- ISSN : 1882-6687
- CiNii Articles ID : 110009598053
- SCOPUS ID : 82455181567