2011年6月
Clock Line Considerations for an SFQ Large Scale Reconfigurable Data Paths Processor
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY
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- 巻
- 21
- 号
- 3
- 開始ページ
- 809
- 終了ページ
- 813
- 記述言語
- 英語
- 掲載種別
- 研究論文(学術雑誌)
- DOI
- 10.1109/TASC.2010.2092402
- 出版者・発行元
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
We have estimated jitter accumulated in data and clock lines of an SFQ Reconfigurable Data Paths processor and its impact on the operating frequency and identified critical components. In order to prevent performance degradation, we have proposed to divide the processor in several parts clocked separately by an external jitter-free system clock. FIFO buffers and clock controllers inserted between the processor stages are used to synchronize each stage with the next one and as a result the accumulation of jitter is limited to one stage of the processor only. Two versions of a synchronization scheme prototype have been designed for both ISTEC-SRL standard 2.5 kA/cm(2) and advanced 10 kA/cm(2) processes and successfully tested at high speed.
- リンク情報
- ID情報
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- DOI : 10.1109/TASC.2010.2092402
- ISSN : 1051-8223
- Web of Science ID : WOS:000291050500167