2012年4月
A C-Testable Multiple-Block Carry Select Adder
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
- ,
- ,
- 巻
- E95D
- 号
- 4
- 開始ページ
- 1084
- 終了ページ
- 1092
- 記述言語
- 英語
- 掲載種別
- 研究論文(学術雑誌)
- DOI
- 10.1587/transinf.E95.D.1084
- 出版者・発行元
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
We propose a C-testable multiple-block carry select adder with respect to the cell fault model. Full adders and 2:1 multiplexers are considered as cells. By an additional external input, we obtain a C-testable carry select adder. We only modify the least significant position of each block. The adder is testable with a test set consisting of 16 patterns regardless of the size of each block and the number of blocks. This is the minimum test set for the adder. We show two gate-level implementations of the adder which are testable with a test set of 9 patterns and 7 patterns respectively, with respect to the single stuck-at fault model.
- リンク情報
- ID情報
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- DOI : 10.1587/transinf.E95.D.1084
- ISSN : 1745-1361
- CiNii Articles ID : 10030942151
- Web of Science ID : WOS:000302834400018