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本文へのリンクあり
2020年7月17日

Radiation Damage Effects on Double-SOI Pixel Sensors for X-ray Astronomy

Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
  • Kouichi Hagino
  • Keigo Yarita
  • Kousuke Negishi
  • Kenji Oono
  • Mitsuki Hayashida
  • Masatoshi Kitajima
  • Takayoshi Kohmura
  • Takeshi G. Tsuru
  • Takaaki Tanaka
  • Hiroyuki Uchida
  • Kazuho Kayama
  • Yuki Amano
  • Ryota Kodama
  • Ayaki Takeda
  • Koji Mori
  • Yusuke Nishioka
  • Masataka Yukumoto
  • Takahiro Hida
  • Yasuo Arai
  • Ikuo Kurachi
  • Tsuyoshi Hamano
  • Hisashi Kitamura
  • 全て表示

978
DOI
10.1016/j.nima.2020.164435

The X-ray SOI pixel sensor onboard the FORCE satellite will be placed in the
low earth orbit and will consequently suffer from the radiation effects mainly
caused by geomagnetically trapped cosmic-ray protons. Based on previous studies
on the effects of radiation on SOI pixel sensors, the positive charges trapped
in the oxide layer significantly affect the performance of the sensor. To
improve the radiation hardness of the SOI pixel sensors, we introduced a
double-SOI (D-SOI) structure containing an additional middle Si layer in the
oxide layer. The negative potential applied on the middle Si layer compensates
for the radiation effects, due to the trapped positive charges. Although the
radiation hardness of the D-SOI pixel sensors for applications in high-energy
accelerators has been evaluated, radiation effects for astronomical application
in the D-SOI sensors has not been evaluated thus far. To evaluate the radiation
effects of the D-SOI sensor, we perform an irradiation experiment using a 6-MeV
proton beam with a total dose of ~ 5 krad, corresponding to a few tens of years
of in-orbit operation. This experiment indicates an improvement in the
radiation hardness of the X- ray D-SOI devices. On using an irradiation of 5
krad on the D-SOI device, the energy resolution in the full-width half maximum
for the 5.9-keV X-ray increases by 7 $\pm$ 2%, and the chip output gain
decreases by 0.35 $\pm$ 0.09%. The physical mechanism of the gain degradation
is also investigated; it is found that the gain degradation is caused by an
increase in the parasitic capacitance due to the enlarged buried n-well.

リンク情報
DOI
https://doi.org/10.1016/j.nima.2020.164435
arXiv
http://arxiv.org/abs/arXiv:2007.08718
URL
http://arxiv.org/abs/2007.08718v1
URL
http://arxiv.org/pdf/2007.08718v1 本文へのリンクあり
Scopus
https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85088747111&origin=inward
Scopus Citedby
https://www.scopus.com/inward/citedby.uri?partnerID=HzOxMe3b&scp=85088747111&origin=inward
ID情報
  • DOI : 10.1016/j.nima.2020.164435
  • ISSN : 0168-9002
  • arXiv ID : arXiv:2007.08718
  • SCOPUS ID : 85088747111

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