A simple VLSI particle-induced fault simulator has been proposed where the mappings of the effect of particles to defects or to faults are modeled. The simulator allows us to predict the entire yield of VLSI and also to analyze the bottleneck processing step and faults. In the simulator, particles with spherical shape are generated in the production equipment for each VLSI processing step and are deposited on the wafer. The simulator accepts as inputs (a) layout description of the VLSI design under analysis in GDS II format, (b) production flow data, (c) planned layer thickness data, and (d) particle parameters for each production equipment. The predictor was applied to a 16-Mbit DRAM production process to show its validity. (C) 1999 ACRS. Published by Elsevier Science Ltd. All rights reserved.