1999年
TAT-and cost-reduction strategies in LSI manufacturing test process
10th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, ASMC 1999
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- 開始ページ
- 59
- 終了ページ
- 63
- 記述言語
- 英語
- 掲載種別
- DOI
- 10.1109/ASMC.1999.798182
- 出版者・発行元
- Institute of Electrical and Electronics Engineers Inc.
Testing strategies in the test process composed of a wafer-probe testing phase, an LSI assembly and packaging phase, and a final testing phase are discussed to reduce the turn around time and costs with the manufacturing yield as a parameter through an event-driven simulation analysis. Three screening strategies considered in the wafer-probe testing phase are exhaustive testing, checkerboard sample testing and no wafer testing [NW]. The application of the simulation program to a test process for one-chip microcomputers showed that the NW strategy becomes effective in a yield range of larger than 70%. The simulation allows one to predict the effectiveness of the testing strategy with the manufacturing yield as a parameter.
- ID情報
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- DOI : 10.1109/ASMC.1999.798182
- SCOPUS ID : 33646218629