MISC

1996年8月

Automatic layout recycling based on layout description and linear programming

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
  • Y Shigehiro
  • ,
  • T Nagata
  • ,
  • Shirakawa, I
  • ,
  • Arungsrisangchai, I
  • ,
  • H Takahashi

15
8
開始ページ
959
終了ページ
967
記述言語
英語
掲載種別
DOI
10.1109/43.511575
出版者・発行元
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

When a fabrication process is renewed, of practical importance is how to make the best use of layout resources so far accumulated for old fabrication processes. The present paper describes an automatic recycling system for layout data once used dedicatedly for functional cells of the standard-cell level, The main process of this system is i) to transform given layout data into a layout description format expressed in parameters associated with shapes, sizes, and locations of layout elements, and then ii) to resynthesize an optimal layout in accordance with a new set of design rules by means of a graph theoretic linear programming approach. A part of implementation results is also shown.

リンク情報
DOI
https://doi.org/10.1109/43.511575
CiNii Articles
http://ci.nii.ac.jp/naid/80009122458
Web of Science
https://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=JSTA_CEL&SrcApp=J_Gate_JST&DestLinkType=FullRecord&KeyUT=WOS:A1996UY95500010&DestApp=WOS_CPL
ID情報
  • DOI : 10.1109/43.511575
  • ISSN : 0278-0070
  • CiNii Articles ID : 80009122458
  • Web of Science ID : WOS:A1996UY95500010

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