苫米地 宣裕

VLSI architecture based on packet data transfer scheme and its application 

Proceedings of 2005 IEEE International Symposium on Circuits and Systems pp.1786-1789 2005年  

Pipelined architecture of high-speed RSA encryption processor using redundant binary arithmetic and table-look-up 

Proceedings of 2004 IEEE International Conference on Electrical and Computer Engineering Vol. 3, pp.593-595 2004年  

Reconfigurable architecture of high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers 

Proceedings of 2004 IEEE International Conference on High Performance Computing 2004年  

Design of a search processor for competitively traveling robots 共著 

Proc. of 2004 IEEE Mediterranean Conference on Control and Automation MoM1-A-5 2004年  

Design of a search processor for competition-type intelligent robots 共著 

Proc. of 2004 IEEE International Conference on Mechatronics T4A-2 2004年  

Design of a search processor for competitively traveling robots 

Proc. of 2004 IEEE Meiditerranean Conference on Control and Automation MoM1-A-5 2004年  

Design of a search processor for competition-type intelligent robots 

Proc. of 2004 IEEE international Conference on Mechatronics T4A-2 2004年  

Design of a parallel VLSI processor for tele-robot systems based on dynamin reconfigration of power supply voltages 共著 

Proc. of 2003 SICE Annual Conference pp.2638-2643 2003年  

Design of a parallel VLSI processor for tele-robot systems based on dynamic reconfiguration of power supply voltages 

Proc. of2003 SICE Annual Conference pp.2638-2643 2003年  

Pipelined-design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers 共著 

Proc. of IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering PP. 412-415 2002年  

Pipelined-design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers 

Proc. of IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering PP. 412-415 2002年  

Multi-layer printed wiring board with built-in soldering heater and 3D implementation of dynamically reconfigurable highly parallel processors 共著 

Proc. of International Conference on Control, Automation and Systems 2001 2001年  

Defect-tolerance design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers 共著 

Proc. of IEEE International Conference on Electronics, Circuits and Systems PP. 267-271 2001年  

冗長2進剰余テーブルに基づく高速RSA暗号プロセッサの構成法 共著 

電子情報通信学会 論文誌D-Ⅰ Vol. J84-D-Ⅰ No. 5 PP. 423-432 2001年  

Multi-layer printed wiring board with built-in soldering heater and 3D implementation of dynamically reconfigurable highly parallel processors 

Proc. of International Conference on Control, Automation and Systems 2001 2001年  

Defect-tolerance design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers 

Proc. of IEEE International Conference on Electronics, Circuits and Systems PP. 267-271 2001年  

Design of a high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers 共著 

Proc. of IEEE International Symposium on Circuits and Systems V697-V700 2000年